Datasheet

Rev. 3.00, 03/04, page 544 of 830
16.3.12 SERIRQ Control Register 2 (SIRQCR2)
The SIRQCR2 register contains status bits that specify an SERIRQ interrupt source.
The SIRQCR2 register is initialized to H'00 by a reset or in hardware standby mode.
R/W
Bit Bit Name Initial Value Slave Host Description
7 IEDIR3 0 R/W  Interrupt Enable Direct Mode 3
Specifies whether SERIRQ interrupt sources (SMI,
HIRQ6, and HIRQ9 to HIRQ11) of LPC channel 3
are generated in relation to OBF or only by the host
interrupt enable bit.
0: The host interrupt is requested when both the
host interrupt enable bit and corresponding OBF
are set to 1
1: The host interrupt is requested when the host
interrupt enable bit is set to 1
6 to 0  All 0 R/W 
Reserved
The initial value should not be changed.