Datasheet

Rev. 3.00, 03/04, page 540 of 830
R/W
Bit Bit Name Initial Value Slave Host Description
7 IRQ11E3 0 R/W  Host IRQ11 Interrupt Enable 3
Enables or disables a HIRQ11 interrupt request
when OBF3A is set by an ODR3 write.
0: HIRQ11 interrupt request by OBF3A and
IRQ11E3 is disabled
[Clearing conditions]
• Writing 0 to IRQ11E3
• LPC hardware reset, LPC software reset
• Clearing OBF3A to 0 (when IEDIR3 = 0)
1: [When IEDIR3 = 0]
HIRQ11 interrupt request by setting OBF3A to 1
is enabled
[When IEDIR3 = 1]
HIRQ11 interrupt is requested.
[Setting condition]
• Writing 1 after reading IRQ11E3 = 0
6 IRQ10E3 0 R/W  Host IRQ10 Interrupt Enable 3
Enables or disables a HIRQ10 interrupt request
when OBF3A is set by an ODR3 write.
0: HIRQ10 interrupt request by OBF3A and
IRQ10E3 is disabled
[Clearing conditions]
• Writing 0 to IRQ10E3
• LPC hardware reset, LPC software reset
• Clearing OB3FA to 0 (when IEDIR3 = 0)
1: [When IEDIR3 = 0]
HIRQ10 interrupt request by setting OBF3A to 1
is enabled
[When IEDIR3 = 1]
HIRQ10 interrupt is requested.
[Setting condition]
• Writing 1 after reading IRQ10E3 = 0