Datasheet

Rev. 3.00, 03/04, page 539 of 830
R/W
Bit Bit Name Initial Value Slave Host Description
0 IRQ1E1 0 R/W  Host IRQ1 Interrupt Enable 1
Enables or disables a HIRQ1 interrupt request when
OBF1 is set by an ODR1 write.
0: HIRQ1 interrupt request by OBF1 and IRQ1E1 is
disabled
[Clearing conditions]
• Writing 0 to IRQ1E1
• LPC hardware reset, LPC software reset
• Clearing OBF1 to 0
1: HIRQ1 interrupt request by setting OBF1 to 1 is
enabled
[Setting condition]
• Writing 1 after reading IRQ1E1 = 0
16.3.11 SERIRQ Control Register 1 (SIRQCR1)
The SIRQCR1 register contains status bits that enable or disable an SERIRQ interrupt request.
The SIRQCR1 register is initialized to H'00 by a reset or in hardware standby mode.