Datasheet

Rev. 3.00, 03/04, page 509 of 830
16.2 Input/Output Pins
Table 16.1 lists the input and output pins of the LPC.
Table 16.1 Pin Configuration
Name Abbreviation Port I/O Function
LPC address/
data 3 to 0
LAD3 to LAD0 PE3 to
PE0
I/O Serial (4-signal-line) transfer cycle
type/address/data signals,
synchronized with LCLK
LPC frame LFRAME PE4 Input*
1
Transfer cycle start and forced
termination signal
LPC reset LRESET PE5 Input*
1
LPC interface reset signal
LPC clock LCLK PE6 Input 33 MHz PCI clock signal
Serialized
interrupt request
SERIRQ PE7 I/O*
1
Serialized host interrupt request
signal, synchronized with LCLK
(SMI, HIRQ1, HIRQ6, HIRQ9 to
HIRQ12)
LSCI general
output
LSCI PD0 Output*
1,
*
2
General output
LSMI general
output
LSMI PD1 Output*
1,
*
2
General output
PME general
output
PME PD2 Output*
1,
*
2
General output
GATE A20 GA20 PD3 Output*
1,
*
2
A20 gate control signal output
LPC clock run CLKRUN PD4 I/O*
1,
*
2
LCLK restart request signal in case
of serial host interrupt request
LPC power-down LPCPD PD5 Input*
1
LPC module shutdown signal
Notes: 1. Pin state monitoring input is possible in addition to the LPC interface control
input/output function.
2. Only 0 can be output. If 1 is output, the pin goes to the high-impedance state, so an
external resistor is necessary to pull the signal up to VCC.