Datasheet

Rev. 3.00, 03/04, page 508 of 830
Figure 16.1 shows a block diagram of the LPC.
Module data bus
Cycle detection
Serial ← parallel conversion
Address match
SYNC output
Parallel → serial conversion
Control logic
Internal interrupt
control
HICR0 to HICR4:
LADR12H, 12L:
LADR3H, 3L:
IDR1 to IDR3:
ODR1 to ODR3:
STR1 to STR3:
TWR0MW:
TWR0SW:
TWR1 to TWR15:
SIRQCR0 to SIRQCR2:
HISEL:
Host interface control register 0 to 4
LPC channel 1, 2 address register 12H, 12L
LPC channel 3 address register 3H, 3L
Input data register 1 to 3
Output data register 1 to 3
Status register 1 to 3
Bidirectional data register 0MW
Bidirectional data register 0SW
Bidirectional data registers 1 to 15
SERIRQ control registers 0 to 2
Host interface select register
[Legend]
TWR1 to 15
IDR3
IDR2
IDR1
LADR1
LADR2
LADR3
LADR12
SIRQCR0
SIRQCR1
SIRQCR2
HISEL
TWR0MW
TWR1 to 15
ODR3
ODR2
ODR1
STR3
STR2
STR1
HICR0
HICR1
HICR2
HICR3
HICR4
TWR0SW
LSCIE
LSCIB
LSCI input
PD0 I/O
LSMIE
LSMIB
LSMI input
PD1 I/O
PMEE
PMEB
PME input
PD2 I/O
LAD0 to
LAD3
SERIRQ
CLKRU
N
LSCI
LSMI
PME
LPCPD
LFRAME
LRESET
LCLK
IBFI1
IBFI2
IBFI3
ERRI
BTDTR
FIFO
(IN)
BTDTR
FIFO
(OUT)
GA20
Serial → parallel conversion
Figure 16.1 Block Diagram of LPC