Datasheet

Rev. 3.00, 03/04, page 491 of 830
The acknowledge bit may indicate specific events such as completion of receive data processing
for some receiving devices, and for other receiving devices, the acknowledge bit may be held to 1,
indicating no specific events.
The I
2
C bus format provides for selection of the slave device and transfer direction by means of
the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication
of the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out
in conjunction with CPU processing by means of interrupts.
Table 15.9 shows some examples of processing using the DTC. These examples assume that the
number of transfer data bytes is known in slave mode.
Table 15.9 Examples of Operation Using the DTC
Item
Master Transmit
Mode
Master Receive
Mode
Slave Transmit
Mode
Slave Receive
Mode
Slave address +
R/W bit
transmission/
reception
Transmission by
DTC (ICDR write)
Transmission by
CPU (ICDR write)
Reception by
CPU (ICDR read)
Reception by CPU
(ICDR read)
Dummy data
read
 Processing by
CPU (ICDR read)
 
Actual data
transmission/
reception
Transmission by
DTC (ICDR write)
Reception by
DTC (ICDR read)
Transmission by
DTC (ICDR write)
Reception by DTC
(ICDR read)
Dummy data
(H'FF) write
  Processing by
DTC (ICDR write)

Last frame
processing
Not necessary Reception by
CPU (ICDR read)
Not necessary Reception by CPU
(ICDR read)
Transfer request
processing after
last frame
processing
1st time: Clearing
by CPU
2nd time: Stop
condition issuance
by CPU
Not necessary Automatic clearing
on detection of
stop condition
during
transmission of
dummy data (H'FF)
Not necessary
Setting of
number of DTC
transfer data
frames
Transmission:
Actual data count
+ 1 (+1 equivalent
to slave address +
R/W bits)
Reception: Actual
data count
Transmission:
Actual data count
+ 1 (+1 equivalent
to dummy data
(H'FF))
Reception: Actual
data count