Datasheet

Rev. 3.00, 03/04, page 470 of 830
SDA
(master output)
SDA
(slave output)
21
R/W
436587
12
9
A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6
ICDRE
IRTR
ICDRT
Note: Do not set ICDR
during this period.
SCL
(master output)
Start condition generation
Slave address
Data 1
Data 1
[9] ICDR write
[9] IRIC clear
[6] ICDR write
[6] IRIC clear
[4] BBSY set to 1 and
SCP cleared to 0
(start condition issuance)
User processing
Interrupt
request
Interrupt
request
Address + R/W
IRIC
[7]
[5]
ICDRS
Data 1
Address + R/W
Figure 15.8 Operation Timing Example in Master Transmit Mode (MLS = WAIT = 0)
SDA
(master output)
SDA
(slave output)
21436587989
A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 0
ICDRE
IRTR
ICDR
SCL
(master output)
Stop condition issuance
Data 2
[9] ICDR write
[9] IRIC clear
[12] IRIC clear
[11] ACKB read
[12] BBSY set to 1 and
SCP cleared to 0
(Stop condition issuance)
IRIC
A
[10]
[7]
Data 1
Data 1
Data 2
User processing
Figure 15.9 Stop Condition Issuance Operation Timing Example in Master Transmit Mode
(MLS = WAIT = 0)