Datasheet

Rev. 3.00, 03/04, page 418 of 830

UART frame

Data

IR frame

Data

0000 011 11 1

Transmission

Reception

Bit

cycle

Pulse width is 1.6 µs to

3/16 bit cycle

Start

bit

Stop

bit

Stop

bit

Start

bit

Figure 14.37 IrDA Transmission and Reception

Reception: During reception, IR frames are converted to UART frames using the IrDA interface

before inputting to SCI_1.

Data of level 0 is output each time a high-level pulse is detected and data of level 1 is output when

no pulse is detected in a bit cycle. If a pulse has a high-level width of less than 1.41 µs, the

minimum width allowed, the pulse is recognized as level 0.

High-Level Pulse Width Selection: Table 14.13 shows possible settings for bits IrCKS2 to

IrCKS0 (minimum pulse width), and this LSI's operating frequencies and bit rates, for making the

pulse width shorter than 3/16 times the bit rate in transmission.