Datasheet

Rev. 3.00, 03/04, page 1 of 830
Section 1 Overview
1.1 Overview
• High-speed H8S/2000 central processing unit with an internal 16-bit architecture
Upward-compatible with H8/300 and H8/300H CPUs on an object level
Sixteen 16-bit general registers
65 basic instructions
• Various peripheral functions
Data transfer controller (DTC)
8-bit PWM timer (PWM)
14-bit PWM timer (PWMX)
16-bit free-running timer (FRT)
8-bit timer (TMR)
Watchdog timer (WDT)
Asynchronous or clocked synchronous serial communication interface (SCI)
CRC operation circuit (CRC)
I
2
C bus interface (IIC)
LPC interface (LPC)
8-bit D/A converter
10-bit A/D converter
Boundary scan (JTAG)
Clock pulse generator
• On-chip memory
ROM Type Model ROM RAM Remarks
Flash memory
Version
HD64F2168 256 kbytes 40 kbytes
Flash memory
Version
HD64F2167 384 kbytes 40 kbytes
Flash memory
Version
HD64F2166 512 kbytes 40 kbytes
• General I/O ports
I/O pins: 106
Input-only pins: 9
• Supports various power-down states
• Compact package