Datasheet

Rev. 3.00, 03/04, page 373 of 830
Table 14.6 BRR Settings for Various Bit Rates (Clock Synchronous Mode)
Operating Frequency φ (MHz)
8 10 16 20 24 32
Bit
Rate
(bit/s)
n N n N n N n N n N n N
110
250 3 124   3 249
500 2 249   3 124     3 249
1k 2 124   2 249     3 124
2.5k 1 199 1 249 2 99 2 124 2 149 2 199
5k 1 99 1 124 1 199 1 249 2 74 2 99
10k 0 199 0 249 1 99 1 124 1 149 1 199
25k 0 79 0 99 0 159 0 199 0 239 0 179
50k 0 39 0 49 0 79 0 99 0 119 0 159
100k 0 19 0 24 0 39 0 49 0 59 0 79
250k 0 7 0 9 0 15 0 19 0 23 0 31
500k 0 3 0 4 0 7 0 9 0 11 0 15
1M 0 1 0 3 0 4 0 5 0 7
2.5M 0 0* 0 1
5M 0 0*
[Legend]
: Setting prohibited.
 : Can be set, but there will be a degree of error.
*: Continuous transfer or reception is not possible.
Table 14.7 Maximum Bit Rate with External Clock Input (Clock Synchronous Mode)
φ (MHz)
External Input
Clock (MHz)
Maximum Bit
Rate (bit/s) φ (MHz)
External Input
Clock (MHz)
Maximum Bit
Rate (bit/s)
6 1.0000 1000000.0 16 2.6667 2666666.7
8 1.3333 1333333.3 18 3.0000 3000000.0
10 1.6667 1666666.7 20 3.3333 3333333.3
12 2.0000 2000000.0 25 4.1667 4166666.7
14 2.3333 2333333.3 33 5.5000 5500000.0