Datasheet

Rev. 3.00, 03/04, page 354 of 830
RxD0/
RxD2
TxD0/
TxD2
SSE0I/
SSE2I
C/A
CKE1
SSE
SCK0/
SCK2
Clock
External clock
φ
φ
/4
φ /16
φ /64
TEI
TXI
RXI
ERI
RSR:
RDR:
TSR:
TDR:
SMR:
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
SCR:
SSR:
SCMR:
BRR:
SEMR:
Serial control register
Serial status register
Smart card mode register
Bit rate register
Serial enhanced mode register
SCMR
SSR
SCR
SMR
SEMR
Transmission/
reception control
Baud rate
generator
Average transfer
rate generator
BRR
Module data bus
RDR
TSRRSR
Parity generation
[Legend]
TDR
Parity check
Bus interface
Internal data bus
Figure 14.2 Block Diagram of SCI_0 and SCI_2