Datasheet

Rev. 3.00, 03/04, page 341 of 830
Bit Bit Name Initial Value R/W Description
5 TME 0 R/W Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and is
initialized to H'00.
4  0 R/W Reserved
The initial value should not be changed.
3 RST/NMI 0 R/W Reset or NMI
Selects to request an internal reset or an NMI interrupt
when TCNT has overflowed.
0: An NMI interrupt is requested
1: An internal reset is requested
2 to 0 CKS2 to
CKS0
All 0 R/W Clock Select 2 to 0
Select the clock source to be input to TCNT. The
overflow frequency for φ = 33 MHz is enclosed in
parentheses.
000: φ/2 (frequency: 15.5 µs)
001: φ/64 (frequency: 496.5 µs)
010: φ/128 (frequency: 993.0 µs)
011: φ/512 (frequency: 4.0 ms)
100: φ/2048 (frequency: 15.9 ms)
101: φ/8192 (frequency: 63.6 ms)
110: φ/32768 (frequency: 254.2 ms)
111: φ/131072 (frequency: 1.02 s)
Note: * Only 0 can be written, to clear the flag.