Datasheet

Rev. 3.00, 03/04, page 332 of 830
12.9.3 Conflict between TCOR Write and Compare-Match
If a compare-match occurs during the T
2
state of a TCOR write cycle as shown in figure 12.15, the
TCOR write takes priority and the compare-match signal is disabled. With TMR_X, a TICR input
capture conflicts with a compare-match in the same way as with a write to TCORC. In this case
also, the input capture takes priority and the compare-match signal is disabled.
φ
Address TCOR address
Internal write signal
TCNT
TCOR N
M
T
1
T
2
TCOR write cycle by CPU
TCOR write data
N N + 1
Compare-match signal
Disabled
Figure 12.15 Conflict between TCOR Write and Compare-Match