Datasheet

Rev. 3.00, 03/04, page 331 of 830
12.9.2 Conflict between TCNT Write and Increment
If a TCNT input clock is generated during the T
2
state of a TCNT write cycle as shown in figure
12.14, the write takes priority and the counter is not incremented.
φ
Address TCNT address
Internal write signal
TCNT input clock
TCNT N M
T
1
T
2
TCNT write cycle by CPU
Counter write data
Figure 12.14 Conflict between TCNT Write and Increment