Datasheet

Rev. 3.00, 03/04, page 330 of 830
12.9 Usage Notes
12.9.1 Conflict between TCNT Write and Counter Clear
If a counter clear signal is generated during the T
2
state of a TCNT write cycle as shown in
figure 12.13, the counter clear takes priority and the write is not performed.
φ
Address TCNT address
Internal write signal
Counter clear signal
TCNT N
H'00
T
1
T
2
TCNT write cycle by CPU
Figure 12.13 Conflict between TCNT Write and Counter Clear