Datasheet

Rev. 3.00, 03/04, page 313 of 830
Table 12.2 Clock Input to TCNT and Count Condition (cont)
TCR STCR
Channel
CKS2 CKS1 CKS0 ICKS1 ICKS0
Description
TMR_Y 0 1 1   Increments at falling edge of internal
clock φ/2048
1 0 0   Setting prohibited
0 0 0   Disables clock input
0 0 1   Increments at falling edge of internal
clock φ
TMR_X
0 1 0   Increments at falling edge of internal
clock φ/2
0 1 1   Increments at falling edge of internal
clock φ/4
1 0 0   Setting prohibited
1 0 1   Increments at rising edge of external
clock
Common
1 1 0   Increments at falling edge of external
clock
1 1 1   Increments at both rising and falling
edges of external clock.
Note: * If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock
input is set as the TCNT_0 compare-match signal simultaneously, a count-up clock
cannot be generated. Simultaneous setting of these conditions should therefore be
avoided.