Datasheet

Rev. 3.00, 03/04, page 307 of 830
External clock Internal clock
Clock X
Clock Y
Compare match AX
Compare match AY
Clear X
TMOY
TMRIY
TCORA_Y
Comparator A_Y
Comparator B_Y
Comparator C
TCOR_Y
TCR_Y
TISR
TCORA1_X
Comparator A_X
TCNT_X
Comparator B_X
TCORB_Y TCORB_X
TICRR
TICRF
TICR
TCORC
TCSR_X
TCR_X
TMCIY
TCNT_Y
Overflow X
Overflow Y
Compare match BX
Compare match BY
Compare match C
Input capture
TMOX
TMRIX
Select clock
Control logic
Internal bus
[Legend]
Interrupt signals
Clear Y
TMR_X
φ, φ/2, φ/4
TMR_Y
φ/4, φ/256, φ/2048
CMIAX
CMIBX
OVIX
CMIAY
CMIBY
OVIY
ICIX
TCORA_Y:
TCORB_Y:
TCNT_Y:
TCSR_Y:
TCR_Y:
TISR:
TCORA_X:
TCORB_X:
TCNT_X:
TCSR_X:
TCR_X:
TICR:
TCORC:
TICRR:
TICRF:
TMCIX
Time constant register A_Y
Time constant register B_Y
Timer counter_Y
Timer control / status register_Y
Timer control register_Y
Timer input select register
Time constant register A_X
Time constant register B_X
Timer counter_X
Timer control / status register_X
Timer control register_X
Input capture register
Tme constant registerC
Input capture register R
Input capture register F
Figure 12.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X)