Datasheet

Rev. 3.00, 03/04, page 306 of 830
External clock Internal clock
TMR_0
φ/2, φ/8, φ/32, φ/64, φ/256, φ/1024
Clock 1
Clock 0
Compare match A1
Compare match A0
Clear 1
CMIA0
CMIB0
OVI0
CMIA1
CMIB1
OVI1
TMO0
TMRI0
TCORA_0
Comparator A_0
Comparator B_0
TCORB_0
TCSR_0
TCR_0
TCORA_1
Comparator A_1
TCNT_1
Comparator B_1
TCORB_1
TCSR_1
TCR_1
TMCI0
TMCI1
TCNT_0
Overflow 1
Overflow 0
Compare match B1
Compare match B0
TMO1
TMRI1
Select clock
Control logic
Internal bus
[Legend]
Interrupt signals
Clear 0
TMR_1
φ/2, φ/8, φ/64, φ/128, φ/1024, φ/2048
TCORA_0:
TCORB_0:
TCNT_0:
TCSR_0:
TCR_0:
TCORA_1:
TCORB_1:
TCNT_1:
TCSR_1:
TCR_1:
Time constant register A_0
Time constant register B_0
Timer counter_0
Timer control/status register_0
Timer control register_0
Time constant register A_1
Time constant register B_1
Timer counter_1
Timer control/status register_1
Timer control register_1
Figure 12.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)