Datasheet

Rev. 3.00, 03/04, page 300 of 830
11.7.2 Conflict between FRC Write and Increment
If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes
priority and FRC is not incremented. Figure 11.18 shows the timing for this type of conflict.
φ
Address FRC address
Internal write
signal
FRC input
clock
Write data
FRC N
M
T
1
T
2
Write cycle of FRC
Figure 11.18 Conflict between FRC Write and Increment