Datasheet

Rev. 3.00, 03/04, page 294 of 830
Input capture
signal
FTIA
φ
T
1
T
2
CPU read cycle of ICRA or ICRC
Figure 11.10 Buffered Input Capture Timing (BUFEA = 1)
11.5.6 Timing of Input Capture Flag (ICF) Setting
The input capture flag, ICFA to ICFD, is set to 1 by the input capture signal. The FRC value is
simultaneously transferred to the corresponding input capture register (ICRA to ICRD). Figure
11.11 shows the timing of setting the ICFA to ICFD flag.
Input capture
signal
φ
ICFA to ICFD
ICRA to ICRD
FRC
N
N
Figure 11.11 Timing of Input Capture Flag (ICFA to ICFD) Setting