Datasheet

Rev. 3.00, 03/04, page 271 of 830
PCSR Fixed DADR Bits
PWCKX0
PWCKX1 Bit Data
C B A
CKS
Reso-
lution
T
(µs) CFS
Base
Cycle
Conver-
sion
Cycle
TL/TH
(OS = 0/OS = 1)
Accuracy
(Bits)
D
A3
D
A2
D
A1
D
A0
Conversion
Cycle (ms)*
0 1 1 1 7.76 0 496.48 127.10 14 127.10
(µs) (ms) 12 0 0 31.78
/2.0kHz
Always low/high output
DA13 to 0 = H'0000 to H'00FF
(Data value) × T
DA13 to 0 = H'0100 to H'3FFF
10 0 0 0 0 7.94
1 1985.94 127.10 14 127.10
(µs) (ms) 12 0 0 31.78
(φ/256) /0.5kHz
Always low/high output
DA13 to 0 = H'0000 to H'003F
(Data value) × T
DA13 to 0 = H'0040 to H'3FFF
10 0 0 0 0 7.94
1 0 0 1 31.03 0 1.99 508.40 14 508.40
(ms) (ms) 12 0 0 127.10
/503.5Hz
Always low/high output
DA13 to 0 = H'0000 to H'00FF
(Data value) × T
DA13 to 0 = H'0100 to H'3FFF
10 0 0 0 0 31.78
1 7.94 508.40 14 508.40
(ms) (ms) 12 0 0 127.10
(φ/1024) /125.9Hz
Always low/high output
DA13 to 0 = H'0000 to H'003F
(Data value) × T
DA13 to 0 = H'0040 to H'3FFF
10 0 0 0 0 31.78
1 0 1 1 124.12 0 7.94 2.03 14 2033.60
(ms) (s) 12 0 0 508.40
/125.9Hz
Always low/high output
DA13 to 0 = H'0000 to H'00FF
(Data value) × T
DA13 to 0 = H'0100 to H'3FFF
10 0 0 0 0 127.10
1 31.78 2.03 14 2033.60
(ms) (s) 12 0 0 508.40
(φ/4096) /31.5Hz
Always low/high output
DA13 to 0 = H'0000 to H'003F
(Data value) × T
DA13 to 0 = H'0040 to H'3FFF
10 0 0 0 0 127.10
1 1 0 1 496.48 0 31.78 8.13 14 8134.41
(ms) (s) 12 0 0 2033.60
/31.5Hz
Always low/high output
DA13 to 0 = H'0000 to H'00FF
(Data value) × T
DA13 to 0 = H'0100 to H'3FFF
10 0 0 0 0 508.40
1 127.10 8.13 14 8134.41
(ms) (s) 12 0 0 2033.60
(φ/16384) /7.9Hz
Always low/high output
DA13 to 0 = H'0000 to H'003F
(Data value) × T
DA13 to 0 = H'0040 to H'3FFF
10 0 0 0 0 508.40
1 1 1 1 Setting
prohibited
         
Note: * Indicates the conversion cycle when specific DA3 to DA0 bits are fixed.