Datasheet

Rev. 3.00, 03/04, page 267 of 830
10.3.4 Peripheral Clock Select Register (PCSR)
PCSR and the CKS bit of DACR select the operating speed.
Bit Bit Name Initial Value R/W Description
7
6
PWCKX1B
PWCKX1A
0
0
R/W
R/W
PWMX_1 Clock Select
These bits select a clock cycle with the CKS bit of
DACR of PWMX_1 being 1.
See table 10.2.
5
4
PWCKX0B
PWCKX0A
0
0
R/W
R/W
PWMX_0 Clock Select
These bits select a clock cycle with the CKS bit of
DACR of PWMX_0 being 1.
See table 10.2.
3 PWCKX1C 0 R/W PWMX_1 Clock Select
This bit selects a clock cycle with the CKS bit of DACR
of PWMX_1 being 1.
See table 10.2.
2
1
PWCKB
PWCKA
0
0
R/W
R/W
PWM Clock Select B and A
See section 9.3.5, Peripheral Clock Select Register
(PCSR).
0 PWCKX0C 0 R/W PWMX_0 Clock Select
This bit selects a clock cycle with the CKS bit of DACR
of PWMX_0 being 1.
See table 10.2.
Table 10.2 Clock Select of PWMX_1 and PWMX_0
PWCKX0C
PWCKX1C
PWCKX0B
PWCKX1B
PWCKX0A
PWCKX1A Resolution (T)
0 0 0 Operates on the system clock cycle (t
cyc
) x 2
0 0 1 Operates on the system clock cycle (t
cyc
) x 64
0 1 0 Operates on the system clock cycle (t
cyc
) x 128
0 1 1 Operates on the system clock cycle (t
cyc
) x 256
1 0 0 Operates on the system clock cycle (t
cyc
) x 1024
1 0 1 Operates on the system clock cycle (t
cyc
) x 4096
1 1 0 Operates on the system clock cycle (t
cyc
) x 16384
1 1 1 Setting prohibited