Datasheet

Rev. 3.00, 03/04, page 262 of 830
10.2 Input/Output Pins
Table 10.1 lists the PWMX (D/A) module input and output pins.
Table 10.1 Pin Configuration
Name Abbreviation I/O Function
PWMX output pin 0 PWX0 Output PWM timer pulse output of PWMX_0 channel A
PWMX output pin 1 PWX1 Output PWM timer pulse output of PWMX_0 channel B
PWMX output pin 2 PWX2 Output PWM timer pulse output of PWMX_1 channel A
PWMX output pin 3 PWX3 Output PWM timer pulse output of PWMX_1 channel B
10.3 Register Descriptions
The PWMX (D/A) module has the following registers. The PWMX (D/A) registers are assigned to
the same addresses with other registers. The registers are selected by the IICE bit in the serial
timer control register (STCR). For details on the module stop control register, see section 23.1.3,
Module Stop Control Register H, L, and A (MSTPCRH, MSTPCRL, MSTPCRA).
• PWMX (D/A) counter (DACNT)
• PWMX (D/A) data register A (DADRA)
• PWMX (D/A) data register B (DADRB)
• PWMX (D/A) control register (DACR)
• Peripheral clock select register (PCSR)
Note: The same addresses are shared by DADRA and DACR, and by DADRB and DACNT.
Switching is performed by the REGS bit in DACNT or DADRB.