Datasheet

Rev. 3.00, 03/04, page 255 of 830
Table 9.3 Resolution, PWM Conversion Period, and Carrier Frequency when φ = 33 MHz
Internal Clock
Frequency Resolution
PWM Conversion
Period Carrier Frequency
φ 30 ns 7.76 µs 2063 kHz
φ/2 61 ns 15.52 µs 1031 kHz
φ/4 121 ns 31.03 µs 515.6 kHz
φ/8 242 ns 62.06 µs 257.8 kHz
φ/16 485 ns 124.12 µs 128.9 kHz
9.3.2 PWM Data Registers 15 to 0 (PWDR15 to PWDR0)
PWDR are 8-bit readable/writable registers. The PWM has sixteen PWM data registers. Each
PWDR specifies the duty cycle of the basic pulse to be output, and the number of additional
pulses. The value set in PWDR corresponds to a 0 or 1 ratio in the conversion period. The upper
four bits specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. The
lower four bits specify how many extra pulses are to be added within the conversion period
comprising 16 basic pulses. Thus, a specification of 0/256 to 255/256 is possible for 0/1 ratios
within the conversion period. For 256/256 (100%) output, port output should be used.
9.3.3 PWM Data Polarity Registers A and B (PWDPRA and PWDPRB)
Each PWDPR selects the PWM output phase.
• PWDPRA
Bit Bit Name
Initial
Value R/W Description
7 to 0 OS7 to OS0 All 0 R/W Output Select 7 to 0
These bits select the PWM output phase. Bits OS7 to OS0
correspond to outputs PW7 to PW0.
0: PWM direct output (PWDR value corresponds to high width
of output)
1: PWM inverted output (PWDR value corresponds to low
width of output)