Datasheet

Rev. 3.00, 03/04, page 253 of 830
9.3.1 PWM Register Select (PWSL)
PWSL is used to select the input clock and the PWM data register.
Bit Bit Name
Initial
Value R/W Description
7
6
PWCKE
PWCKS
0
0
R/W PWM Clock Enable
PWM Clock Select
These bits, together with bits PWCKB and PWCKA in PCSR,
select the internal clock input to TCNT in the PWM. For
details, see table 9.2.
The resolution, PWM conversion period, and carrier frequency
depend on the selected internal clock, and can be obtained
from the following equations.
Resolution (minimum pulse width) = 1/internal clock frequency
PWM conversion period = resolution × 256
Carrier frequency = 16/PWM conversion period
With a 33 MHz system clock (φ), the resolution, PWM
conversion period, and carrier frequency are as shown in table
9.3.
5 — 1 R Reserved
This bit is always read as 1 and cannot be modified.
4 — 0 R Reserved
This bit is always read as 0 and cannot be modified.