Datasheet

PWM0802A_000020021100 Rev. 3.00, 03/04, page 251 of 830
Section 9 8-Bit PWM Timer (PWM)
This LSI has an on-chip pulse width modulation (PWM) timer with sixteen outputs. Sixteen output
waveforms are generated from a common time base, enabling PWM output with a high carrier
frequency to be produced using pulse division.
9.1 Features
• Operable at a maximum carrier frequency of 2.06 kHz using pulse division (at 33 MHz
operation)
• Duty cycles from 0 to 100% with 1/256 resolution (100% duty realized by port output)
• Direct or inverted PWM output, and PWM output enable/disable control
Figure 9.1 shows a block diagram of the PWM timer.
P10/PW0
P11/PW1
P12/PW2
P13/PW3
P14/PW4
P15/PW5
P16/PW6
P17/PW7
P20/PW8
P21/PW9
P22/PW10
P23/PW11
P24/PW12
P25/PW13
P26/PW14
P27/PW15
Comparator 0
Comparator 1
Comparator 2
Comparator 3
Comparator 4
Comparator 5
Comparator 6
Comparator 7
Comparator 8
Comparator 9
Comparator 10
Comparator 11
Comparator 12
Comparator 13
Comparator 14
Comparator 15
PWDR0
PWDR1
PWDR2
PWDR3
PWDR4
PWDR5
PWDR6
PWDR7
PWDR8
PWDR9
PWDR10
PWDR11
PWDR12
PWDR13
PWDR14
PWDR15
PWSL
φ
φ/8
PWDPRB
PWOERB
P2DDR
P2DR
PTCNT0
PWDPRA
PWOERA
P1DDR
P1DR
[Legend]
PWSL:
PWDR:
PWDPRA:
PWDPRB:
PWOERA:
PWOERB:
PWM register select
PWM data register
PWM data polarity register A
PWM data polarity register B
PWM output enable register A
PWM output enable register B
PCSR
φ/2
φ/4
φ/16
Port/PWM output control
Module
data bus
Internal
data bus
Bus interface
Select
clock
Clock
counter
Internal clock
Peripheral clock select register
Port 1 data direction register
Port 2 data direction register
Port 1 data register
Port 2 data register
Port control register 0
PCSR:
P1DDR:
P2DDR:
P1DR:
P2DR:
PTCNT0:
Figure 9.1 Block Diagram of PWM Timer