Datasheet

Rev. 3.00, 03/04, page 246 of 830
• PE0/LAD0
The pin function is switched as shown below according to the LPC enabled/disabled and the
PE0DDR.
LPC Disabled Enabled
PE0DDR 0 1 
Pin Function PE0 input pin PE0 output pin LAD0 input/output pin
8.15 Port F
Port F is a 3-bit multi-function input/output port supporting the following register set.
• Port F data direction register (PFDDR)
• Port F output data register (PFODR)
• Port F input data register (PFPIN)
8.15.1 Port F Data Direction Register (PFDDR)
PFDDR is used to specify the input/output attribute of each pin of port F.
Bit Bit Name Initial Value R/W Description
7 to 3    Reserved
2 PF2DDR 0 W
1 PF1DDR 0 W
0 PF0DDR 0 W
When the given bit of PFDDR is set to 1, the
corresponding pin of port F will function as an output
port, and when the bit is cleared to 0, the port pin will
function as an input port.
This register is assigned to the same address as that
of PFPIN. When this address is read, the port F states
are returned.
8.15.2 Port F Output Data Register (PFODR)
PFODR stores output data for the port F pins.
Bit Bit Name Initial Value R/W Description
7 to 3    Reserved. When this bit is read, an undefined value is
returned.
2 PF2ODR 0 R/W
1 PF1ODR 0 R/W
0 PF0ODR 0 R/W
The PFODR register stores the output data for the
pins that are used a general output port.