Datasheet

Rev. 3.00, 03/04, page 245 of 830
• PE5/LRESET
The pin function is switched as shown below according to the LPC enabled/disabled and the
PE5DDR.
LPC Disabled Enabled
PE5DDR 0 1 
Pin Function PE5 input pin PE5 output pin LRESET input pin
• PE4/LFRAME
The pin function is switched as shown below according to the LPC enabled/disabled and the
PE4DDR.
LPC Disabled Enabled
PE4DDR 0 1 
Pin Function PE4 input pin PE4 output pin LFRAME input pin
• PE3/LAD3
The pin function is switched as shown below according to the LPC enabled/disabled and the
PE3DDR.
LPC Disabled Enabled
PE3DDR 0 1 
Pin Function PE3 input pin PE3 output pin LAD3 input/output pin
• PE2/LAD2
The pin function is switched as shown below according to the LPC enabled/disabled and the
PE2DDR.
LPC Disabled Enabled
PE2DDR 0 1 
Pin Function PE2 input pin PE2 output pin LAD2 input/output pin
• PE1/LAD1
The pin function is switched as shown below according to the LPC enabled/disabled and the
PE1DDR.
LPC Disabled Enabled
PE1DDR 0 1 
Pin Function PE1 input pin PE1 output pin LAD1 input/output pin