Datasheet

Rev. 3.00, 03/04, page 234 of 830
• PB5/ EVENT13
PB5DDR 0 1
Event counter*
1
Disable Enable 
Pin function PB5 input pin EVENT13 input pin PB5 output pin
• PB4/EVENT12
PB4DDR 0 1
Event counter*
1
Disable Enable 
Pin function PB4 input pin EVENT12 input pin PB4 output pin
• PB3/EVENT11
PB3DDR 0 1
Event counter*
1
Disable Enable 
Pin function PB3 input pin EVENT11 input pin PB3 output pin
• PB2/EVENT10
PB2DDR 0 1
Event counter*
1
Disable Enable 
Pin function PB2 input pin EVENT10 input pin PB2 output pin
• PB1/EVENT9
PB1DDR 0 1
Event counter*
1
Disable Enable 
Pin function PB1 input pin EVENT9 input pin PB1 output pin
• PB0/EVENT8
PB0DDR 0 1
Event counter*
1
Disable Enable 
Pin function PB0 input pin EVENT8 input pin PB0 output pin
Note: For event counter setting, refer to section 7, Data Transfer Controller (DTC).