Datasheet

Rev. 3.00, 03/04, page 225 of 830
• P92/CPCS1
The pin function is switched as shown below according to the combination of the operating
mode, the CPCSE bit in BCR2 of BSC, and the P92DDR bit.
Operating
Mode
Extended Mode Single-Chip Mode
CPCSE 0 1 
P92DDR 0 1  0 1
Pin function P92 input pin P92 output pin CPCS1 output pin P92 input pin P92 output pin
• P91/AH
The pin function is switched as shown below according to the combination of the operating
mode, the ADMXE bit of SYSCR2, and the P91DDR bit.
Operating
Mode
Extended Mode Single-Chip Mode
ADMXE 0 1 
P91DDR 0 1  0 1
Pin function P91 input pin P91 output pin AH output pin P91 input pin P91 output pin
• P90/LWR
The pin function is switched as shown below according to the combination of the operating
mode, the ABW and ABW256 bits in WSCR, the ABWCP bit in BCR2, and the P90DDR bit.
Operating
Mode
Extended Mode Single-Chip Mode
ABW,
ABW256,
ABWCP
All 1 One bit is set as
0

P90DDR 0 1  0 1
Pin function P90 input pin P90 output pin LWR output pin P90 input pin P90 output pin