Datasheet

Rev. 3.00, 03/04, page 223 of 830
8.9.2 Port 9 Data Register (P9DR)
P9DR stores output data for the port 9 pins.
Bit Bit Name Initial Value R/W Description
7 P97DR 0 R/W
6 P96DR Undefined* R
5 P95DR 0 R/W
4 P94DR 0 R/W
3 P93DR 0 R/W
2 P92DR 0 R/W
1 P91DR 0 R/W
0 P90DR 0 R/W
P9DR stores output data for the port 9 pins that are
used as the general output port except for bit 6.
If a port 9 read is performed while the P9DDR bits are
set to 1, the P9DR values are read. If a port 9 read is
performed while the P9DDR bits are cleared to 0, the
pin states are read.
Note: The initial value of bit 6 is determined in accordance with the P96 pin state.
8.9.3 Pin Functions
The relationship between the operating mode, register setting values, and pin functions are as
follows.
• P97/WAIT/CS256
The pin function is switched as shown below according to the combination of the operating
mode, the CS256E bit in SYSCR, the WMS1 bit in WSCR, the WMS21 bit in WSCR2, and
the P97DDR bit.
Operating
Mode
Extended Mode Single-Chip Mode
WMS1,
WMS21
All 0 One bit is set as
1

CS256E 0 1  
P97DDR 0 1   0 1
Pin function P97 input
pin
P97 output
pin
CS256 output
pin
WAIT input pin P97 input
pin
P97output
pin