Datasheet

Rev. 3.00, 03/04, page 208 of 830
Sampling clock
Port data
register
Sampling clock selection
t
φ/2, φ/32, φ/512, φ/8192,
φ/32768,
φ/65536,
φ/131072,
φ/2621446
Latch
Pin
input
Latch Latch
Matching detection circuit
t
Figure 8.1 Noise Canceler Circuit
P6n Input
1 expected
P6nDR
0 expected
P6nDR
Figure 8.2 Noise Canceler Operation