Datasheet

Rev. 3.00, 03/04, page 207 of 830
8.6.6 Noise Canceler Mode Control Register (P6NCMC)
P6NCMC controls whether 1 or 0 is expected for the input signal to port 6 in bit units.
Bit Bit Name Initial Value R/W Description
7 P67NCMC 1 R/W
6 P66NCMC 1 R/W
5 P65NCMC 1 R/W
4 P64NCMC 1 R/W
3 P63NCMC 1 R/W
2 P62NCMC 1 R/W
1 P61NCMC 1 R/W
0 P60NCMC 1 R/W
In 16 bit bus mode in extended mode:
Port 6 operates as the data pin (D7 to D0).
In other mode:
1 expected: 1 is stored in the port data register while 1
is input stably
0 expected: 0 is stored in the port data register while 0
is input stably
8.6.7 Noise Canceler Cycle Setting Register (P6NCCS)
P6NCCS controls the sampling cycles of the noise canceler.
Bit Bit Name Initial Value R/W Description
7 to 3  All undefined R/W Reserved. The read data is undefined. The initial
value should not be changed.
2 NCCK2 0 R/W
1 NCCK1 0 R/W
0 NCCK0 0 R/W
These bits set the sampling cycles of the noise
canceler.
000: 0.06 µs φ/2
001: 0.97 µs φ/32
010: 15.5 µs φ/512
011: 248.2 µs φ/8192
100: 993.0 µs φ/32768
101: 2.0 ms φ/65536
110: 4.0 ms φ/131072
111: 7.9 ms φ/262144