Datasheet

Rev. 3.00, 03/04, page 200 of 830
8.5 Port 5
Port 5 is an 8-bit I/O port. Port 5 pins also function as interrupt input pins, the PWMX output pin,
SCI_0, SCI_1, and SCI_2 input/output pins. Port 5 has the following registers.
• Port 5 data direction register (P5DDR)
• Port 5 data register (P5DR)
8.5.1 Port 5 Data Direction Register (P5DDR)
The individual bits of P5DDR specify input or output for the pins of port 5.
Bit Bit Name Initial Value R/W Description
7 P57DDR 0 W
6 P56DDR 0 W
5 P55DDR 0 W
4 P54DDR 0 W
3 P53DDR 0 W
2 P52DDR 0 W
1 P51DDR 0 W
0 P50DDR 0 W
If port 5 pins are specified for use as the general I/O
port, the corresponding port 5 pins are output ports
when the P5DDR bits are set to 1, and input ports
when cleared to 0.
8.5.2 Port 5 Data Register (P5DR)
P5DR stores output data for the port 5 pins.
Bit Bit Name Initial Value R/W Description
7 P57DR 0 R/W
6 P56DR 0 R/W
5 P55DR 0 R/W
4 P54DR 0 R/W
3 P53DR 0 R/W
2 P52DR 0 R/W
1 P51DR 0 R/W
0 P50DR 0 R/W
P5DR stores output data for the port 5 pins that are
used as the general output port.
If a port 5 read is performed while the P5DDR bits are
set to 1, the P5DR values are read. If a port 5 read is
performed while the P5DDR bits are cleared to 0, the
pin states are read.