Datasheet

Rev. 3.00, 03/04, page 172 of 830
Table 7.9 Number of States Required for Each Execution Status
Object to be Accessed
On-Chip RAM
(H'FFEC00 to
H'FFEFFF)
On-Chip RAM
(On-chip RAM area
other than H'FFEC00 to
H'FFEFFF)
On-
Chip
ROM
On-Chip
I/O
Registers
External Devices
Bus width 32 16 16 8 16 8 8 16 16
Access states 1 1 1 2 2 2 3 2 3
Vector read S
I
— — 1 — — 4 6 + 2m 2 3 + m Execution
status
Register
information
read/write S
J
1 — — — — — — — —
Byte data read S
K
1 1 1 2 2 2 3 + m 2 3 + m
Word data read
S
K
1 1 1 4 2 4 6 + 2m 2 3 + m
Byte data write S
L
1 1 1 2 2 2 3 + m 2 3 + m
Word data write
S
L
1 1 1 4 2 4 6 + 2m 2 3 + m
Internal operation
S
M
1 1 1 1 1 1 1 1 1
The number of execution states is calculated from using the formula below. Note that Σ is the sum
of all transfers activated by one activation source (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · S
I
+ Σ (J · S
J
+ K · S
K
+ L · S
L
) + M · S
M
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from on-chip ROM to an internal I/O register, then the time required for the
DTC operation is 13 states. The time from activation to the end of data write is 10 states.