Datasheet

Rev. 3.00, 03/04, page 147 of 830
6.7 Idle Cycle
When this LSI accesses the external address space, it can insert a 1-state idle cycle (T
I
) between
bus cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is
possible, for example, to avoid data collisions between ROM with a long output floating time, and
high-speed memory and I/O interfaces.
If an external write occurs after an external read while the ICIS bit is set to 1 in BCR, an idle cycle
is inserted at the start of the write cycle.
Figure 6.29 shows examples of idle cycle operation. In these examples, bus cycle A is a read cycle
for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In figure 6.29 (a),
with no idle cycle inserted, a collision occurs in bus cycle B between the read data from ROM and
the CPU write data. In figure 6.29 (b), an idle cycle is inserted, thus preventing data collision.
T
1
Address bus
φ
Bus cycle A
Data bus
T
2
T
3
T
1
T
2
Bus cycle B
Long output floating time
Data collision
(a) No idle cycle insertion
T
1
Address bus
φ
Bus cycle A
Data bus
T
2
T
3
T
I
T
1
Bus cycle B
(b) Idle cycle insertion
T
2
WR WR
RD RD
Figure 6.29 Examples of Idle Cycle Operation
Table 6.17 shows the pin states in an idle cycle.
Table 6.17 Pin States in Idle Cycle
Pins Pin State
A23 to A0 Contents of immediately following bus cycle
D15 to D0 High impedance
AS, IOS, CS256, CPCS1 High
RD High
HWR, LWR High