Datasheet

Rev. 3.00, 03/04, page 146 of 830
T
1
Address bus
φ
Data bus
T
2
T
1
T
1
Full access
RD
Burst access
Only lower
address changes
Read data Read data Read data
AS/IOS
(IOSE = 0)
Figure 6.28 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0)
6.6.2 Wait Control
As with the basic bus interface, program wait insertion or pin wait insertion using the WAIT pin is
possible in the initial cycle (full access) of the burst ROM interface. For details, see section 6.5.5,
Wait Control. Wait states cannot be inserted in a burst cycle.