Datasheet

Rev. 3.00, 03/04, page 141 of 830
Read Cycle
Address Data Data
Write Cycle
T
1
T
2
T
3
T
AW
T
5
T
DSW
T
4
T
1
T
2
T
3
T
AW
T
5
T
DSW
T
4
Address
CPCS1
CS256
IOS
AH
RD
HWR
LWR
AD7 to AD0
Data
Data
AD15 to AD8
φ
Address Address
Address Address
Data
Data
Figure 6.24 Bus Timing for 16-Bit, 3-State Access Space (3) (Word Access)
6.5.5 Wait Control
When accessing the external address space, this LSI can extend the bus cycle by inserting one or
more wait states (T
W
). There are three ways of inserting wait states: Program wait insertion, pin
wait insertion using the WAIT pin, and the combination of program wait and the WAIT pin.
(1) In Normal Extended Mode
(a) Program Wait Mode: A specified number of wait states T
W
are always inserted between the
T
2
state and T
3
state when accessing the external address space. The number of wait states T
W
is
specified by the settings of the WC1 and WC0 bits in WSCR (the WC11 and WC10 bits in
WSCR2 for the 256-kbyte extended area, and the WC21 and WC20 bits in WSCR2 for the CP
extended area).
(b) Pin Wait Mode: A specified number of wait states T
W
are always inserted between the T
2
state
and T
3
state when accessing the external address space. The number of wait states T
W
is specified
by the settings of the WC1 and WC0 bits (the WC21 and WC20 bits for the CP extended area). If
the WAIT pin is low at the falling edge of φ in the last T
2
or T
W
state, another T
W
state is inserted.
If the WAIT pin is held low, T
W
states are inserted until it goes high.
Pin wait mode is useful when inserting four or more T
W
states, or when changing the number of T
W
states to be inserted for each external device.