Datasheet

Rev. 3.00, 03/04, page 140 of 830
(4) 16-Bit, 3-State Data Access Space: Figures 6.22 to 6.24 show bus timings for a 16-bit, 3-state
access space. When a 16-bit access space is accessed, the upper half (AD15 to AD8) of the data
bus is used for even addresses, and the lower half (AD7 to AD0) for odd addresses. Wait states
can be inserted.
Read Cycle
Address Data Data
Write Cycle
T
1
T
2
T
3
T
AW
T
5
T
DSW
T
4
T
1
T
2
T
3
T
AW
T
5
T
DSW
T
4
Address
CPCS1
CS256
IOS
AH
RD
HWR
LWR
AD7 to AD0
AD15 to AD8
φ
Address Address
Address Address
Data Data
Figure 6.22 Bus Timing for 16-Bit, 3-State Access Space (1) (Even Byte Access)
Read Cycle
Address Data Data
Write Cycle
T
1
T
2
T
3
T
AW
T
5
T
DSW
T
4
T
1
T
2
T
3
T
AW
T
5
T
DSW
T
4
Address
CPCS1
CS256
IOS
AH
RD
HWR
LWR
AD7 to AD0
AD15 to AD8
φ
Address Address
Address Address
Data Data
Figure 6.23 Bus Timing for 16-Bit, 3-State Access Space (2) (Odd Byte Access)