Datasheet

Rev. 3.00, 03/04, page 137 of 830
Read Cycle
Address Data Data
Write Cycle
T
1
T
2
T
3
T
AW
T
4
Address
T
1
T
2
T
3
T
AW
T
4
CPCS1
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
AD7 to AD0
φ
Address Address
Data Data
Address Address
Figure 6.16 Bus Timing for 16-Bit, 2-State Access Space (1) (Even Byte Access)
Read Cycle
Address
Data Address Data
Write Cycle
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
CPCS1
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
AD7 to AD0
φ
Address Address
Data Data
Address Address
Figure 6.17 Bus Timing for 16-Bit, 2-State Access Space (2) (Even Byte Access)