Datasheet

Rev. 3.00, 03/04, page 136 of 830
(2) 8-Bit, 3-State Data Access Space: Figure 6.15 shows the bus timing for an 8-bit, 3-state
access space. When an 8-bit access space is accessed, the upper half (AD15 to AD8) of the data
bus is used. Wait states can be inserted.
Read Cycle
Address Data Data
Data
Write Cycle
T
1
T
2
T
3
T
AW
T
5
T
DSW
T
4
T
1
T
2
T
3
T
AW
T
5
T
DSW
T
4
Address
CPCS1
CS256
IOS
AH
RD
HWR
AD15 to AD8
φ
Address Address
Data
Figure 6.15 Bus Timing for 8-Bit, 3-State Access Space
(3) 16-Bit, 2-State Data Access Space: Figures 6.16 to 6.21 show bus timings for a 16-bit, 2-state
access space. When a 16-bit access space is accessed, the upper half (AD15 to AD8) of the data
bus is used for even addresses, and the lower half (AD7 to AD0) for odd addresses. Wait states
cannot be inserted.