Datasheet

Rev. 3.00, 03/04, page 135 of 830
6.5.4 Basic Operation Timing in Address-Data Multiplex Extended Mode
(1) 8-Bit, 2-State Data Access Space: Figures 6.13 and 6.14 show the bus timing for an 8-bit, 2-
state access space. When an 8-bit access space is accessed, the upper half (AD15 to AD8) of the
data bus is used. Wait states cannot be inserted.
Read Cycle
Address Data
Data
Address Data
Write Cycle
T
1
T
2
T
3
T
AW
T
4
T
1
T
2
T
3
T
AW
T
4
φ
CPCS1
CS256
IOS
AH
RD
HWR
AD15 to AD8
Address Address
Data
Figure 6.13 Bus Timing for 8-Bit, 2-State Access Space
Read Cycle
Address Data Address Data
Write Cycle
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
CPCS1
CS256
IOS
AH
RD
HWR
AD15 to AD8
φ
Address Address
Data
Data
Figure 6.14 Bus Timing for 8-Bit, 2-State Access Space