Datasheet

Rev. 3.00, 03/04, page 133 of 830
Bus cycle
T
1
T
2
Address bus
φ
AS (IOSE = 0)
RD
D15 to D8
Invalid
D7 to D0
Valid
Read
*
HWR
LWR
D15 to D8
Undefined
D7 to D0
Valid
Write
High level
T
3
IOS (IOSE = 1)
CS256 (CS256E = 1)
CPCS1 (CPCSE = 1)
Note: * For external address space access, this signal is not output when the 256-kbyte expansion area
is accessed with CS256E = 1 and when the CP expansion area is accessed with CPCSE = 1.
Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access)