Datasheet

Rev. 3.00, 03/04, page 106 of 830
Bit Bit Name
Initial
Value R/W Description
3 BRSTS0 0 R/W Valid only in the normal extended mode.
Burst Cycle Select 0
Selects the number of words that can be accessed by burst
access via the burst ROM interface.
0: Max, 4 words
1: Max, 8 words
2  0 R/W Reserved
The initial value should not be changed.
1
0
IOS1
IOS0
1
1
R/W
R/W
IOS Select 1 and 0
Select the address range where the IOS signal is output.
See table 6.15.
6.3.2 Bus Control Register 2 (BCR2)
BCR2 is used to specify the access mode for the CP extended area.
Bit Bit Name
Initial
Value R/W Description
7, 6  All 0 R/W Reserved
The initial value should not be changed.
5 ABWCP 1 R/W CP Extended Area Bus Width Control
Selects the bus width for access to the CP extended area
when the CPCSE bit is set to 1
0: 16-bit bus
1: 8-bit bus
4 ASTCP 1 R/W CP Extended Area Access State Control
Selects the number of states for access to the CP extended
area when the CPCSE bit is set to 1. This bit also enables or
disables wait-state insertion.
[ADMXE = 0] Normal extension
0: 2-state access space. Wait state insertion disabled
1: 3-state access space. Wait state insertion enabled
[ADMXE = 1] Address-data multiplex extension
0: 2-state data access space. Wait state insertion disabled
1: 3-state data access space. Wait state insertion enabled