Datasheet

Rev. 3.00, 03/04, page 104 of 830
6.2 Input/Output Pins
Table 6.1 summarizes the pin configuration of the bus controller.
Table 6.1 Pin Configuration
Symbol I/O Function
AS Output Strobe signal indicating that address output on the address
bus is enabled (when the IOSE bit in SYSCR is cleared to 0).
Note that this signal is not output when the 256-kbyte
extended area is accessed (the CS256E bit in SYSCR is 1)
or when the CP extended area is accessed (the CPCSE bit
in BCR2 is 1).
IOS Output Chip select signal indicating that the IOS extended area is
being accessed (when the IOSE bit in SYSCR is 1).
CPCS1 Output Chip select signal indicating that the CP extended area is
being accessed (when the CPCSE bit in BCR2 is 1).
CS256 Output Chip select signal indicating that the 256-kbyte extended
area is being accessed (when the CS256E bit in SYSCR is
1).
RD Output Strobe signal indicating that the external address space is
being read.
HWR Output Strobe signal indicating that the external address space is
being written to, and the upper half (D15 to D8, AD15 to
AD8) of the data bus is enabled.
LWR Output Strobe signal indicating that the external address space is
being written to, and the lower half (D7 to D0, AD7 to AD0) of
the data bus is enabled.
WAIT Input Wait request signal when accessing the external space.
AH Output Signal indicating address fetch timing when the bus is in
address-data multiplex bus state.
AD15 to AD0 Input/Output Address output and data input/output pins for address-data
multiplex extension.