Datasheet

BSCS200A_000220030700 Rev. 3.00, 03/04, page 101 of 830
Section 6 Bus Controller (BSC)
This LSI has an on-chip bus controller (BSC) that manages the bus width and the number of
access states of the external address space. The BSC also has a bus arbitration function, and
controls the operation of the internal bus masters – CPU and data transfer controller (DTC).
6.1 Features
• Extended modes
Two modes for external extension
Normal extended mode: Normal extension (when the ADMXE bit in SYSCR2 is 0)
Address-data multiplex extended mode: Multiplex extension (when the ADMXE bit in
SYSCR2 is 1)
• Extended area division
Possible in normal extended mode
The external address space can be accessed as basic extended areas.
A 256-kbyte extended area can be set and controlled independently of basic extended areas.
A CP extended area can be set and controlled independently of basic extended areas.
• Address pin reduction
In normal extended mode:
A 256-kbyte extended area from H'F80000 to H'FBFFFF can be selected using 18 address pins
and the CS256 signal.
A CP extended area (8 kbytes, basic mode) from H'FFC000 to H'FFDFFF can be selected
using 13 address pins and the CPCS1 signal.
A 2-kbyte area from H'FFF000 to H'FFF7FF can be selected using six to eleven address pins
and the IOS signal.
In address-data multiplex extended mode:
The external address space can be accessed as the following three extended areas.
H'F80000 to H'F8FFFF 64 kbytes 256-kbyte extended area
H'FFC000 to H'FFDFFF 8 kbytes CP extended area
H'FFF000 to H'FFF7FF 2 kbytes IOS extended area
These areas can be selected using 8 pins or 16 pins, which is a total of address pins and data
input/output pins.
• Control address hold signal and aria select signal polarity
The output polarity of IOS, CS256, CPCS1, and AH can be inverted by the PNCCS and
PNCAH bits in LPWRCR