Datasheet

Rev. 3.00, 03/04, page 94 of 830
Program execution state
Interrupt generated?
NMI
An interrupt with interrupt
control level 1?
IRQ0
IRQ1
IBFI3
IRQ0
IRQ1
IBFI3
UI = 0
Save PC and CCR
I 1, UI 1
Read vector address
Branch to interrupt handling routine
Yes
No
Yes
Yes
Yes
No
No
Yes
No
Yes No
Yes
Yes
No
No
Yes
Yes
No
Hold pending
I = 0 I = 0
Yes
Yes
No
No
Figure 5.7 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt
Control Mode 1
5.6.3 Interrupt Exception Handling Sequence
Figure 5.8 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control mode 0 is set in advanced mode, and the program area and stack area are
in on-chip memory.