To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
User’s Manual The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2168Group 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series H8S/2168 H8S/2167 H8S/2166 HD64F2168 HD64F2167 HD64F2166 Rev.3.00 2004.
Rev. 3.
Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins.
Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Preface This LSI is a microcomputer (MCU) made up of the H8S/2000 CPU with Renesas Technology's original architecture as its core, and the peripheral functions required to configure a system, eg PC server. The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a 16-Mbyte linear address space.
• In order to understand the details of the CPU's functions Read the H8S/2600 Series, H8S/2000 Series Programming Manual. • In order to understand the detailed function of a register whose name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, and initial values of the registers are summarized in section 24, List of Registers.
Rev. 3.
Contents Section 1 Overview............................................................................................1 1.1 1.2 1.3 Overview........................................................................................................................... 1 Internal Block Diagram..................................................................................................... 2 Pin Description.......................................................................................................
2.8 2.9 2.7.9 Effective Address Calculation ............................................................................. 47 Processing States............................................................................................................... 49 Usage Notes ...................................................................................................................... 51 2.9.1 Note on TAS Instruction Usage........................................................................... 51 2.9.
5.5 5.6 5.7 5.4.1 External Interrupts ............................................................................................... 82 5.4.2 Internal Interrupts ................................................................................................ 84 Interrupt Exception Handling Vector Table...................................................................... 85 Interrupt Control Modes and Interrupt Operation ............................................................. 88 5.6.
Section 7 Data Transfer Controller (DTC)........................................................ 149 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 Features............................................................................................................................. 149 Register Descriptions........................................................................................................ 151 7.2.1 DTC Mode Register A (MRA) .....................................................................
Section 8 I/O Ports .............................................................................................177 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 Port 1................................................................................................................................. 183 8.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 183 8.1.2 Port 1 Data Register (P1DR)........................................................................
8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.8.2 Port 8 Data Register (P8DR) ............................................................................... 217 8.8.3 Pin Functions ....................................................................................................... 218 Port 9................................................................................................................................. 222 8.9.1 Port 9 Data Direction Register (P9DDR)...................................
Section 9 8-Bit PWM Timer (PWM).................................................................251 9.1 9.2 9.3 9.4 Features............................................................................................................................. 251 Input/Output Pins .............................................................................................................. 252 Register Descriptions .....................................................................................................
11.5.4 Input Capture Input Timing ................................................................................. 292 11.5.5 Buffered Input Capture Input Timing .................................................................. 293 11.5.6 Timing of Input Capture Flag (ICF) Setting ........................................................ 294 11.5.7 Timing of Output Compare Flag (OCF) setting................................................... 295 11.5.8 Timing of FRC Overflow Flag (OVF) Setting.............
12.9 Usage Notes ...................................................................................................................... 330 12.9.1 Conflict between TCNT Write and Counter Clear............................................... 330 12.9.2 Conflict between TCNT Write and Increment..................................................... 331 12.9.3 Conflict between TCOR Write and Compare-Match........................................... 332 12.9.4 Conflict between Compare-Matches A and B ..............
14.5 14.6 14.7 14.8 14.9 14.10 14.11 14.4.1 Data Transfer Format........................................................................................... 381 14.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ................................................................................................................... 382 14.4.3 Clock.................................................................................................................... 383 14.4.
14.11.1 Features................................................................................................................ 428 14.11.2 Register Descriptions........................................................................................... 428 14.11.3 CRC Operation Circuit Operation........................................................................ 430 14.11.4 Note on CRC Operation Circuit...........................................................................
16.3.8 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15).................................... 528 16.3.9 Status Registers 1 to 3 (STR1 to STR3) .............................................................. 529 16.3.10 SERIRQ Control Register 0 (SIRQCR0)............................................................. 536 16.3.11 SERIRQ Control Register 1 (SIRQCR1)............................................................. 539 16.3.12 SERIRQ Control Register 2 (SIRQCR2)......................................
17.5 Usage Note........................................................................................................................ 594 Section 18 A/D Converter..................................................................................595 18.1 Features............................................................................................................................. 595 18.1.1 Block Diagram..................................................................................................
20.6 20.7 20.8 20.9 20.5.1 Hardware Protection ............................................................................................ 665 20.5.2 Software Protection ............................................................................................. 666 20.5.3 Error Protection ................................................................................................... 666 Switching between User MAT and User Boot MAT........................................................
23.2 23.3 23.4 23.5 23.6 23.7 23.8 23.9 23.10 23.11 23.12 23.1.3 Module Stop Control Registers H, L, and A (MSTPCRH, MSTPCRL, MSTPCRA) ............................................................... 732 23.1.4 Sub-Chip Module Stop Control Registers BH, BL (SUBMSTPBH, SUBMSTPBL) ......................................................................... 734 23.1.5 Sub-Chip Module Stop Control Registers AH, AL (SUBMSTPAH, SUBMSTPAL) .........................................................................
Appendix A. B. C. ......................................................................................................... 817 I/O Port States in Each Pin State....................................................................................... 817 Product Lineup.................................................................................................................. 819 Package Dimensions .........................................................................................................
Figures Section 1 Overview Figure 1.1 Internal Block Diagram ................................................................................................. 2 Figure 1.2 Pin Arrangement (TFP-144).......................................................................................... 3 Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode)..................................................................... 19 Figure 2.2 Stack Structure in Normal Mode ..............................................
Section 6 Bus Controller (BSC) Figure 6.1 Block Diagram of Bus Controller.............................................................................. 103 Figure 6.2 IOS Signal Output Timing ........................................................................................ 123 Figure 6.3 Access Sizes and Data Alignment Control (8-bit Access Space).............................. 124 Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space) ............................ 125 Figure 6.
Figure 7.11 DTC Operation Timing (Example of Chain Transfer) ............................................ 171 Section 8 I/O Ports Figure 8.1 Noise Canceler Circuit .............................................................................................. 208 Figure 8.2 Noise Canceler Operation.......................................................................................... 208 Section 9 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 8-Bit PWM Timer (PWM) Block Diagram of PWM Timer ...............
Section 12 8-Bit Timer (TMR) Figure 12.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)............................................ 306 Figure 12.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X).......................................... 307 Figure 12.3 Pulse Output Example ............................................................................................. 322 Figure 12.4 Count Timing for Internal Clock Input ................................................................... 323 Figure 12.
Figure 14.11 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit)................................................... 389 Figure 14.12 Sample Serial Reception Flowchart (1)................................................................. 391 Figure 14.12 Sample Serial Reception Flowchart (2)................................................................. 392 Figure 14.13 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)..
Figure 14.47 Figure 14.48 Figure 14.49 Figure 14.50 MSB-First Data Transmission............................................................................... 430 LSB-First Data Reception ..................................................................................... 431 MSB-First Data Reception .................................................................................... 432 LSB-First and MSB-First Transmit Data ..............................................................
Figure 15.29 Notes on Reading Master Receive Data ................................................................ 500 Figure 15.30 Flowchart for Start Condition Issuance Instruction for Retransmission and Timing............................................................................................................. 501 Figure 15.31 Stop Condition Issuance Timing ........................................................................... 502 Figure 15.32 IRIC Flag Clearing Timing When WAIT = 1 .........
Figure 20.7 Automatic-Bit-Rate Adjustment Operation of SCI ................................................. 639 Figure 20.8 Overview of Boot Mode State Transition Diagram................................................. 641 Figure 20.9 Programming/Erasing Overview Flow.................................................................... 642 Figure 20.10 RAM Map When Programming/Erasing is Executed ........................................... 643 Figure 20.11 Programming Procedure.............................
Figure 25.6 Oscillation Stabilization Timing (Exiting Software Standby Mode)....................... 790 Figure 25.7 External Clock Input Timing................................................................................... 790 Figure 25.8 Timing of External Clock Output Stabilization Delay Time ................................... 791 Figure 25.9 Subclock Input Timing ............................................................................................ 791 Figure 25.10 Reset Input Timing..........
Rev. 3.
Tables Section 1 Overview Table 1.1 Pin Arrangement in Each Operating Mode............................................................... 4 Table 1.2 Pin Functions ............................................................................................................ 9 Section 2 CPU Table 2.1 Instruction Classification ........................................................................................ 31 Table 2.2 Operation Notation .................................................................
Table 5.8 Table 5.9 Number of States in Interrupt Handling Routine Execution Status ........................ 96 Interrupt Source Selection and Clearing Control .................................................... 98 Section 6 Bus Controller (BSC) Table 6.1 Pin Configuration.................................................................................................. 104 Table 6.2 Address Ranges and External Address Spaces ..................................................... 113 Table 6.
Table 8.1 Table 8.1 Table 8.1 Table 8.2 Table 8.3 Table 8.4 Table 8.5 Table 8.6 Table 8.7 Port Functions (cont) ............................................................................................ 180 Port Functions (cont) ............................................................................................ 181 Port Functions (cont) ............................................................................................ 182 Port 1 Input Pull-Up MOS States.................................
Section 14 Serial Communication Interface (SCI, IrDA, and CRC) Table 14.1 Pin Configuration.................................................................................................. 355 Table 14.2 Relationships between N Setting in BRR and Bit Rate B..................................... 369 Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 370 Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 371 Table 14.
Table 16.7 Table 16.8 Table 16.9 Table 16.10 Table 16.11 Table 16.12 Table 16.13 Fast A20 Gate Output Signals............................................................................... 576 Scope of LPC Interface Pin Shutdown ................................................................. 578 Scope of Initialization in Each LPC Interface Mode ............................................ 579 Serial Interrupt Transfer Cycle Frame Configuration .......................................
Section 23 Power-Down Modes Table 23.1 Operating Frequency and Wait Time.................................................................... 730 Table 23.2 LSI Internal States in Each Mode ......................................................................... 737 Section 25 Electrical Characteristics Table 25.1 Absolute Maximum Ratings ................................................................................. 783 Table 25.2 DC Characteristics (1) ...................................................
Section 1 Overview 1.
Package Code Body Size Pin Pitch TQFP-144 TFP-144 16.0 × 16.0 mm 0.
P75/ExIRQ5/AN5 P76/ExIRQ6/AN6/DA0 P77/ExIRQ7/AN7/DA1 AVCC AVref P60/FTCI/KIN0/D0 P61/FTOA/KIN1/D1 P62/FTIA/KIN2/D2 P63/FTIB/KIN3/D3 P64/FTIC/KIN4/D4 P65/FTID/KIN5/D5 66/FTOB/KIN6/D6 P67/KIN7/D7 VCC ETMS ETDO ETDI ETCK ETRST PF2/ExPW2 PF1/ExPW1 PF0/ExPW0 VSS P27/A15/PW15/AD15 P26/A14/PW14/AD14 P25/A13/PW13/AD13 P24/A12/PW12/AD12 P23/A11/PW11/AD11 P22/A10/PW10/AD10 P21/A9/PW9/AD9 P20/A8/PW8/AD8 P17/A7/PW7/AD7 P16/A6/PW6/AD6 Pin Arrangement P15/A5/PW5/AD5 1.3.
1.3.2 Pin Arrangement in Each Operating Mode Table 1.1 Pin No.
Pin No.
Pin No.
Pin No.
Pin No.
1.3.3 Pin Functions Table 1.2 Pin Functions Type Symbol Pin No. I/O Name and Function Power supply VCC 1, 36 86 Input Power supply pins. Connect all these pins to the system power supply. Connect the bypass capacitor between VCC and VSS (near VCC). VCL 13 Input External capacitance pin for internal step-down power. Connect this pin to Vss through an external capacitor (that is located near this pin) to stabilize internal step-down power. VSS 7, 42, 95, 111 139 Input Ground pins.
Type Symbol Pin No. I/O Name and Function Address/ data multiplex bus AD15 to AD8 96 to 103 Input/ Output 8-bit, upper 16-bit bus AD7 to AD0 104 to 110, 112 Bus control WAIT Interrupts Lower 16-bit bus 17 Input Requests insertion of a wait state in the bus cycle when accessing an external 3-state address space. RD 21 Output This pin is low when the external address space is being read.
Type Symbol PWM timer PW15 to (PWM) PW0 ExPW2 to ExPW0 Pin No. I/O Name and Function 96 to 110 112 Output PWM timer pulse output pins. Selectable from which pin of PWn or ExPWn to output PW2 to PW0.
Type Symbol Pin No. I/O Name and Function Keyboard control KIN15 to KIN13 33 to 35 Input KIN12 to KIN8 37 to 41 Input KIN7 to KIN0 85 to 78 Input Matrix keyboard input pins. All pins have a wakeup function. Normally, KIN15 to KIN0 function as key scan inputs, and P17 to P10 and P27 to P20 function as key scan outputs. Thus, at a maximum of 16 outputs x 16 inputs, 256-key matrix can be configured. WUE15 to 128 to 121 Input WUE8 Wake-up event input pins.
Type Symbol Pin No. I/O Name and Function LPC Interface (LPC) LAD3 to LAD0 55 to 58 Input/ Output Transfer cycle type/address/data I/O pins LFRAME 54 Input Input pin indicating transfer cycle start and forced termination LRESET 53 Input LPC reset pin. When this pin is low, a reset state is entered.
Type Symbol Pin No.
Section 2 CPU The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16 Mbytes linear address space, and is ideal for realtime control. This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending on the product. For details on each product, see section 3, MCU Operating Modes. 2.
• Two CPU operating modes Normal mode* Advanced mode Note: * Not available in this LSI. • Power-down state Transition to power-down state by SLEEP instruction Selectable CPU clock speed 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. • Register configuration The MAC register is supported only by the H8S/2600 CPU.
2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers Eight 16-bit extended registers and one 8-bit control register have been added. • Extended address space Normal mode* supports the same 64 kbytes address space as the H8/300 CPU. Advanced mode supports a maximum 16 Mbytes address space. Note: * Not available in this LSI.
2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal* and advanced. Normal mode* supports a maximum 64 kbytes address space. Advanced mode supports a maximum 16 Mbytes address space. The mode is selected by the LSI's mode pins. Note: * Not available in this LSI. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU in normal mode. • Address space Linear access to a maximum address space of 64 kbytes is possible.
H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector (Reserved for system use) (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.1 Exception Vector Table (Normal Mode) SP PC (16 bits) (a) Subroutine Branch SP CCR CCR* PC (16 bits) (b) Exception Handling Note: * Ignored when returning. Figure 2.2 Stack Structure in Normal Mode Rev. 3.
2.2.2 Advanced Mode • Address space Linear access to a maximum address space of 16 Mbytes is possible. • Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as the upper 16-bit segments of 32-bit registers or address registers. • Instruction set All instructions and addressing modes can be used.
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode, the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper eight bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.
2.3 Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64 kbytes address space in normal mode, and a maximum 16 Mbytes (architecturally 4 Gbytes) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, see section 3, MCU Operating Modes.
2.4 Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and an 8-bit condition code register (CCR).
2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched for read, the least significant PC bit is regarded as 0.) 2.4.3 Extended Control Register (EXR) EXR does not affect operation in this LSI.
2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions.
Bit Bit Name Initial Value R/W Description 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: • Add instructions, to indicate a carry • Subtract instructions, to indicate a borrow • Shift and rotate instructions, to indicate a carry The carry flag is also used as a bit accumulator by bit manipulation instructions. 2.4.
2.5 Data Formats The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.9 shows the data formats of general registers.
Data Type Register Number Word data Rn Data Image 15 0 LSB MSB Word data En 15 0 MSB LSB Longword data ERn 31 16 15 MSB En 0 Rn LSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.9 General Register Data Formats (2) Rev. 3.
2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches.
2.6 Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.
2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.
Table 2.3 Data Transfer Instructions Instruction Size*1 Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in this LSI. MOVTPE B Cannot be used in this LSI. POP W/L @SP+ → Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.
Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function ADD B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd SUB ADDX Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Subtraction on immediate data and data in a general register cannot be performed in bytes. Use the SUBX or ADD instruction.
Table 2.4 Arithmetic Operations Instructions (2) Instruction Size* Function DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets the CCR bits according to the result.
Table 2.5 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data.
Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B ∼ (
Table 2.7 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C ⊕ ( of ) → C Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ ∼ ( of ) → C Logically exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
Table 2.8 Branch Instructions Instruction Size Function Bcc – Branches to a specified address if a specified condition is true. The branching conditions are listed below.
Table 2.9 System Control Instructions Instruction Size* Function TRAPA – Starts trap-instruction exception handling. RTE – Returns from an exception-handling routine. SLEEP – Causes a transition to a power-down state. LDC B/W (EAs) → CCR, (EAs) → EXR Moves the memory operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper eight bits are valid.
Table 2.10 Block Data Transfer Instructions Instruction Size Function EEPMOV.B – if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next: EEPMOV.W – if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next: Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. 2.6.
(1) Operation field only op NOP, RTS (2) Operation field and register fields op rm rn ADD.B Rn, Rm (3) Operation field, register fields, and effective address extension op rn rm MOV.B @(d:16, Rn), Rm EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16 Figure 2.11 Instruction Formats (Examples) Rev. 3.
2.7 Addressing Modes and Effective Address Calculation The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic operations instructions can use the register direct and immediate addressing modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect.
2.7.2 Register Indirect—@ERn The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. If the address is a program instruction address, the lower 24 bits are valid and the upper eight bits are all assumed to be 0 (H'00). 2.7.
Table 2.12 Absolute Address Access Ranges Absolute Address Data address Normal Mode* Advanced Mode 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF 32 bits (@aa:32) Program instruction address Note: 2.7.6 * H'000000 to H'FFFFFF 24 bits (@aa:24) Not available in this LSI.
2.7.8 Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand which contains a branch address. The upper bits of the 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode*, H'000000 to H'0000FF in advanced mode). In normal mode*, the memory operand is a word operand and the branch address is 16 bits long.
2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode*, the upper eight bits of the effective address are ignored in order to generate a 16-bit address. Note * Not available in this LSI. Table 2.13 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format op 2 Effective Address Calculation Effective Address (EA) Register direct (Rn) rm Operand is general register contents.
Table 2.13 Effective Address Calculation (2) Addressing Mode and Instruction Format No 5 Effective Address Calculation Effective Address (EA) Absolute address @aa:8 31 @aa:16 31 @aa:24 24 23 16 15 0 31 24 23 0 Don't care abs op 0 H'FFFF Don't care Sign extension abs op 8 7 24 23 Don't care abs op @aa:32 op 31 6 Immediate #xx:8/#xx:16/#xx:32 op 7 0 24 23 Don't care abs Operand is immediate data.
2.8 Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. • Reset state In this state the CPU and on-chip peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state.
End of bus request Bus request Program execution state End of bus request SLEEP instruction with LSON = 0, PSS = 0, SSBY = 1 Bus request Bus-released state End of exception handling SLEEP instruction with LSON = 0, SSBY = 0 Request for exception handling Sleep mode Interrupt request Exception-handling state External interrupt request Software standby mode RES = high Reset state*1 STBY = high, RES = low Hardware standby mode*2 Power-down state*3 Notes: 1.
2.9 Usage Notes 2.9.1 Note on TAS Instruction Usage The TAS instruction is not generated by the Renesas H8S and H8/300 series C/C++ compilers. The TAS instruction can be used as a user-defined intrinsic function. 2.9.2 Note on Bit Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read data in byte units, manipulate the data of the target bit, and write data in byte units.
2.9.3 EEPMOV Instruction 1. EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4*, which starts from the address indicated by ER5, to the address indicated by ER6. ER5 ER6 ER5 + R4* ER6 + R4* 2. Set R4* and ER6 so that the end address of the destination address (value of ER6 + R4*) does not exceed H'00FFFFFF (the value of ER6 must not change from H'00FFFFFF to H'01000000 during execution). ER5 ER6 ER5 + R4* Invalid Note: * For byte transfer R4L is used. Rev. 3.
Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI supports one operating mode (mode 2). The operating mode is determined by the setting of the mode pins (MD2, MD1, and MD0). Table 3.1 shows the MCU operating mode selection. Table 3.1 MCU Operating Mode Selection MCU Operating CPU Operating Mode MD2 MD1 MD0 Mode Description 2 1 1 0 Advanced Extended mode with on-chip ROM Single-chip mode Mode 2 is single-chip mode after a reset.
3.2 Register Descriptions The following registers are related to the operating mode. For details on the bus control register (BCR), see section 6.3.1, Bus Control Register (BCR), and for details on bus control register 2 (BCR2), see section 6.3.2, Bus Control Register 2 (BCR2). • Mode control register (MDCR) • System control register (SYSCR) • Serial timer control register (STCR) 3.2.1 Mode Control Register (MDCR) MDCR is used to set an operating mode and to monitor the current operating mode.
3.2.2 System Control Register (SYSCR) SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode and the detection edge for NMI, enables or disables register access to the on-chip peripheral modules, and enables or disables on-chip RAM address space. Bit Bit Name Initial Value R/W Description 7 CS256E 0 R/W Chip Select 256 Enable Enables or disables P97/WAIT/CS256 pin function in extended mode.
Bit Bit Name Initial Value R/W Description 1 KINWUE 0 R/W Keyboard Control Register Access Enable Enables or disables CPU access for input control registers (KMIMRA, KMIMR6, WUEMR3) of KINn and WUEn pins, input pull-up MOS control register (KMPCR6) of the KINn pin, and registers (TCR_X/TCR_Y, TCSR_X/TCSR_Y, TICRR/TCORA_Y, TICRF/TCORB_Y, TCNT_X/TCNT_Y, TCORC/TISR, TCORA_X, TCORB_X) of 8-bit timers (TMR_X, TMR_Y), 0: Enables CPU access for registers of TMR_X and TMR_Y in an area from H'FFFFF0 to H'FF
Bit Bit Name Initial Value R/W Description 4 IICE 0 R/W IIC Master Enable Enables or disables CPU access for IIC registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR), PWMX registers (DADRAH/DACR, DADRAL, DADRBH/DACNTH, DADRBL/DACNTL), and SCI registers (SMR, BRR, SCMR). 0: SCI_1 registers are accessed in an area from H'FFFF88 to H'FFFF89 and from H'FFFF8E to H'FFFF8F. SCI_2 registers are accessed in an area from H'FFFFA0 to H'FFFFA1 and from H'FFFFA6 to H'FFFFA7.
3.3 Operating Mode Descriptions 3.3.1 Mode 2 The CPU can access a 16 Mbytes address space in advanced mode. The on-chip ROM is enabled. After a reset, the LSI is set to single-chip mode. To access an external address space, bit EXPE in MDCR should be set to 1. Normal extended mode: In extended modes, ports 1 and 2 function as input ports after a reset. Ports 1 and 2 function as an address bus by setting 1 to the corresponding port data direction register (DDR).
Table 3.
3.4 Address Map Figures 3.1 to 3.3 show memory maps in operating mode.
ROM: 384 kbytes, RAM: 40 kbytes Mode 2 (EXPE = 1) Advanced mode Extended mode with on-chip ROM ROM: 384 kbytes, RAM: 40 kbytes Mode 2 (EXPE = 0) Advanced mode Single-chip mode H'000000 H'000000 On-chip ROM H'05FFFF On-chip ROM H'05FFFF Reserved area Reserved area H'07FFFF H'080000 H'F7FFFF H'F80000 H'FBFFFF H'FC0000 H'FEFFFF H'FF0000 H'FF07FF H'FF0800 H'07FFFF External address space 256 kbytes extended area External address space Reserved area H'FF0000 H'FF07FF H'FF0800 Reserved area On-chip RA
ROM: 512 kbytes, RAM: 40 kbytes Mode 2 (EXPE = 1) Advanced mode Extended mode with on-chip ROM H'000000 ROM: 512 kbytes, RAM: 40 kbytes Mode 2 (EXPE = 0) Advanced mode Single-chip mode H'000000 On-chip ROM H'07FFFF H'080000 H'F7FFFF H'F80000 H'FBFFFF H'FC0000 H'FEFFFF H'FF0000 H'FF07FF H'FF0800 On-chip ROM H'07FFFF External address space 256 kbytes extended area External address space Reserved area H'FF0000 H'FF07FF H'FF0800 Reserved area On-chip RAM* (36 kbytes) On-chip RAM (36 kbytes) H'FF97FF H
Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, interrupt, direct transition, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Table 4.
4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Table 4.
Table 4.
4.3 Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-on. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. The chip can also be reset by overflow of the watchdog timer.
Vector fetch Internal processing Prefetch of first program instruction φ RES Internal address bus (1) U (1) L (3) Internal read signal High Internal write signal Internal data bus (2) U (2) L (4) (1) Reset exception handling vector address (1) U = H'000000 (1) L = H'000002 (2) Start address (contents of reset exception handling vector address) (3) Start address ((3) = (2)U + (2)L) (4) First program instruction Figure 4.1 Reset Sequence 4.3.
4.4 Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The sources to start interrupt exception handling are external interrupt sources (NMI, IRQ15 to IRQ0, KIN15 to KIN0, and WUE15 to WUE8) and internal interrupt sources from the on-chip peripheral modules. NMI is an interrupt with the highest priority. For details, see section 5, Interrupt Controller. Interrupt exception handling is conducted as follows: 1.
4.6 Stack Status after Exception Handling Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. Advanced mode SP CCR PC (24 bits) Figure 4.2 Stack Status after Exception Handling Rev. 3.
4.7 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed in words or longwords, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn PUSH.L ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W Rn POP.L ERn (or MOV.W @SP+, Rn) (or MOV.
Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with ICR An interrupt control register (ICR) is provided for setting interrupt priorities. Priority levels can be set for each module for all interrupts except NMI, KIN, and WUE.
CPU INTM1, INTM0 SYSCR NMIEG NMI input NMI input IRQ input IRQ input ISR ISCR IER Interrupt request Vector number Priority level determination KMIMR WUEMR KIN input WUE input I, UI KIN, WUE input CCR Internal interrupt sources SWDTEND to IBFI3 ICR Interrupt controller [Legend] ICR: ISCR: IER: ISR: KMIMR: WUEMR: SYSCR: Interrupt control register IRQ sense control register IRQ enable register IRQ status register Keyboard matrix interrupt mask register Wake-up event interrupt mask register System
5.2 Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Symbol I/O Function NMI Input Nonmaskable external interrupt Rising edge or falling edge can be selected IRQ15 to IRQ0 ExIRQ15 to ExIRQ2 Input Maskable external interrupts Rising edge, falling edge, or both edges, or level sensing, can be selected individually for each pin. Pin of IRQn or ExIRQn to input IRQ15 to IRQ2 interrupts can be selected.
5.3 Register Descriptions The interrupt controller has the following registers. For details on the system control register (SYSCR), see section 3.2.2, System Control Register (SYSCR), and for details on the IRQ sense port select registers (ISSR16, ISSR), see section 8.16.1, IRQ Sense Port Select Register 16 (ISSR16), IRQ Sense Port Select Register (ISSR).
Table 5.2 Correspondence between Interrupt Source and ICR Register Bit Bit Name ICRA ICRB ICRC ICRD 7 ICRn7 IRQ0 A/D converter SCI_0 IRQ8 to IRQ11 6 ICRn6 IRQ1 FRT SCI_1 IRQ12 to IRQ15 5 ICRn5 IRQ2, IRQ3 — SCI_2 — 4 ICRn4 IRQ4, IRQ5 TMR_X IIC_0 — 3 ICRn3 IRQ6, IRQ7 TMR_0 IIC_1 — 2 ICRn2 DTC TMR_1 IIC_2, IIC_3 — 1 ICRn1 WDT_0 TMR_Y LPC — 0 ICRn0 WDT_1 IIC_4, IIC_5 — — [Legend]] n: A to D : Reserved. The write value should always be 0. 5.3.
5.3.3 Break Address Registers A to C (BARA to BARC) The BAR registers specify an address that is to be a break address. An address in which the first byte of an instruction exists should be set as a break address. In normal mode, addresses A23 to A16 are not compared. • BARA Bit Bit Name Initial Value R/W Description 7 to 0 A23 to A16 All 0 R/W Addresses 23 to 16 The A23 to A16 bits are compared with A23 to A16 in the internal address bus.
5.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ15 to IRQ0 or pins ExIRQ15 to ExIRQ2.
• ISCRH Bit Bit Name Initial Value R/W Description 7 6 IRQ7SCB IRQ7SCA 0 0 R/W R/W IRQn Sense Control B IRQn Sense Control A 5 4 IRQ6SCB IRQ6SCA 0 0 R/W R/W 00: Interrupt request generated at low level of IRQn or ExIRQn input 3 2 IRQ5SCB IRQ5SCA 0 0 R/W R/W 01: Interrupt request generated at falling edge of IRQn or ExIRQn input 1 0 IRQ4SCB IRQ4SCA 0 0 R/W R/W 10: Interrupt request generated at rising edge of IRQn or ExIRQn input 11: Interrupt request generated at both falling and ris
5.3.5 IRQ Enable Registers (IER16, IER) The IER registers control the enabling and disabling of interrupt requests IRQ15 to IRQ0. • IER16 Bit Bit Name Initial Value R/W Description 7 to 0 IRQ15E to IRQ8E All 0 R/W IRQn Enable (n = 15 to 8) Bit Bit Name Initial Value R/W Description 7 to 0 IRQ7E to IRQ0E All 0 R/W IRQn Enable (n = 7 to 0) The IRQn interrupt request is enabled when this bit is 1. • IER The IRQn interrupt request is enabled when this bit is 1. Rev. 3.
5.3.6 IRQ Status Registers (ISR16, ISR) The ISR registers are flag registers that indicate the status of IRQ15 to IRQ0 interrupt requests.
5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR6) Wake-Up Event Interrupt Mask Register (WUEMR3) The KMIMR and WUEMR registers enable or disable key-sensing interrupt inputs (KIN15 to KIN0), and wake-up event interrupt inputs (WUE15 to WUE8). The KMIMRA, KMIMR6, and WUEMR3 registers can be accessed when the KINWUE bit in SYSCR is set to 1. See section 3.2.2, System Control Register (SYSCR).
5.4 Interrupt Sources 5.4.1 External Interrupts There are four external interrupts: NMI, IRQ15 to IRQ0, KIN15 to KIN0 and WUE15 to WUE8. These interrupts can be used to restore this LSI from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits.
KIN15 to KIN0 Interrupts, WUE15 to WUE8 Interrupts: Interrupts KIN15 to KIN0 and WUE15 to WUE8 are requested by an input signal at pins KIN15 to KIN0 and WUE15 to WUE8. Interrupts KIN15 to KIN0 and WUE15 to WUE8 have the following features: • Interrupts KIN15 and KIN8, KIN7 to KIN0 and WUE15 to WUE8 each form a group. The interrupt exception handling for an interrupt request from the same group is started at the same vector address.
5.4.2 Internal Interrupts Internal interrupts issued from the on-chip peripheral modules have the following features: • For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that individually select enabling or disabling of these interrupts. When the enable bit for a particular interrupt source is set to 1, an interrupt request is sent to the interrupt controller. • The control level for each interrupt can be set by ICR.
5.5 Interrupt Exception Handling Vector Table Table 5.3 lists interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed. An interrupt control level can be specified for a module to which an ICR bit is assigned.
Table 5.
Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities (cont) Origin of Interrupt Source Name Vector Address Vector Number Advanced Mode IIC_0 IICI0 94 H'000178 ICRC4 IIC_1 IICI1 98 H'000188 ICRC3 IIC_4 IICI4 100 H'000190 ICRB0 IIC_5 IICI5 102 H'000198 LPC ERR1(transfer error, etc.
5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: Interrupt control mode 0 and interrupt control mode 1. Interrupt operations differ depending on the interrupt control mode. NMI interrupts and address break interrupts are always accepted except for in reset state or in hardware standby mode. The interrupt control mode is selected by SYSCR. Table 5.4 shows the interrupt control modes. Table 5.
Interrupt Acceptance Control and 3-Level Control: In interrupt control modes 0 and 1, interrupt acceptance control and 3-level mask control is performed by means of the I and UI bits in CCR and ICR (control level). Table 5.5 shows the interrupts selected in each interrupt control mode. Table 5.
Table 5.6 Operations and Control Signal Functions in Each Interrupt Control Mode Interrupt Acceptance Control Setting Interrupt Control Mode INTM1 INTM0 0 0 0 1 1 3-Level Control Default Priority I UI ICR Determination T (Trace) O IM — PR O — O IM IM PR O — [Legend] O: Interrupt operation control performed IM: Used as an interrupt mask bit PR: Sets priority —: Not used 5.6.
Program execution state Interrupt generated? No Yes Yes NMI No No An interrupt with interrupt control level 1? Hold pending Yes No No IRQ0 IRQ0 Yes No Yes IRQ1 Yes No IRQ1 Yes IBFI3 IBFI3 Yes Yes I=0 No Yes Save PC and CCR I 1 Read vector address Branch to interrupt handling routine Figure 5.5 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0 Rev. 3.
5.6.2 Interrupt Control Mode 1 In interrupt control mode 1, mask control is applied to three levels for IRQ and on-chip peripheral module interrupt requests by comparing the I and UI bits in CCR in the CPU, and the ICR setting. 1. An interrupt request with interrupt control level 0 is accepted when the I bit in CCR is cleared to 0. When the I bit is set to 1, the interrupt request is held pending. EVENTI, KIN, and WUE interrupts are enabled or disabled by the I bit. 2.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority).
Program execution state No Interrupt generated? Yes Yes NMI No No An interrupt with interrupt control level 1? Hold pending Yes IRQ0 Yes No No IRQ0 No Yes IRQ1 No IRQ1 Yes Yes IBFI3 IBFI3 Yes Yes I=0 No I=0 Yes No UI = 0 No Yes Yes Save PC and CCR I 1, UI 1 Read vector address Branch to interrupt handling routine Figure 5.7 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1 5.6.3 Interrupt Exception Handling Sequence Figure 5.
Figure 5.8 Interrupt Exception Handling Rev. 3.00, 03/04, page 95 of 830 (2) (4) (3) (5) (7) (1) Internal data bus (1) (2) (4) Instruction prefetch (3) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) Instruction code (not executed) Instruction prefetch address (Instruction is not executed.
5.6.4 Interrupt Response Times Table 5.7 shows interrupt response times − the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.7 are explained in table 5.8. Table 5.7 No.
5.6.5 DTC Activation by Interrupt The DTC can be activated by an interrupt. In this case, the following options are available: • Interrupt request to CPU • Activation request to DTC • Both of the above For details of interrupt requests that can be used to activate the DTC, see section 7, Data Transfer Controller (DTC). Figure 5.9 shows a block diagram of the DTC and interrupt controller.
Operation Order: If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. Table 5.9 summarizes interrupt source selection and interrupt source clearing control according to the settings of the DTCE bit of DTCERA to DTCERE in the DTC and the DISEL bit of MRB in the DTC. Table 5.
5.7 Usage Notes 5.7.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the instruction.
5.7.2 Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.7.3 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.
Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the bus width and the number of access states of the external address space. The BSC also has a bus arbitration function, and controls the operation of the internal bus masters – CPU and data transfer controller (DTC). 6.
• Multiplex bus interface No Wait Inserted Wait Inserted Address Data Address Data 2 states * 2 states 2 states * (3 + wait) states CP extended area 2 states * 2 states 2 states * (3 + wait) states IOS extended area 2 states * 2 states 2 states * (3 + wait) states 256-kbyte extended area Note: * A wait cycle is inserted by the setting of the WC22 bit. • Basic bus interface 2-state access or 3-state access can be selected for each area. Program wait states can be inserted for each area.
Bus controller External bus control signals Internal control signals BCR BCR2 WSCR WSCR2 Internal data bus Bus mode signal Wait controller WAIT CPU bus request signal Bus arbiter DTC bus request signal CPU bus acknowledge signal DTC bus acknowledge signal [Legend] BCR: BCR2: WSCR: WSCR2: Bus control register Bus control register 2 Wait state control register Wait state control register 2 Figure 6.1 Block Diagram of Bus Controller Rev. 3.
6.2 Input/Output Pins Table 6.1 summarizes the pin configuration of the bus controller. Table 6.1 Pin Configuration Symbol I/O Function AS Output Strobe signal indicating that address output on the address bus is enabled (when the IOSE bit in SYSCR is cleared to 0). Note that this signal is not output when the 256-kbyte extended area is accessed (the CS256E bit in SYSCR is 1) or when the CP extended area is accessed (the CPCSE bit in BCR2 is 1).
6.3 Register Descriptions The following registers are provided for the bus controller. For the system control register (SYSCR), see section 3.2.2, System Control Register (SYSCR). For system control register 2 (SYSCR2), see section 8.6.4, System Control Register 2 (SYSCR2). • • • • Bus control register (BCR) Bus control register 2 (BCR2) Wait state control register (WSCR) Wait state control register 2 (WSCR2) 6.3.
Bit Bit Name Initial Value R/W Description 3 BRSTS0 0 R/W Valid only in the normal extended mode. Burst Cycle Select 0 Selects the number of words that can be accessed by burst access via the burst ROM interface. 0: Max, 4 words 1: Max, 8 words 2 0 R/W Reserved The initial value should not be changed. 1 0 IOS1 IOS0 1 1 R/W R/W IOS Select 1 and 0 Select the address range where the IOS signal is output. See table 6.15. 6.3.
Bit Bit Name Initial Value R/W Description 3 ADFULLE 0 R/W Address Output Full Enable Controls the address output in access to the IOS extended area, 256-kbyte extended area, or CP extended area. See section 8, I/O Ports. This is not supported while ADMXE = 1. 2 EXCKS 0 R/W External Extension Clock Select Selects the operating clock used in external extended area access. 0: Medium-speed clock is selected as the operating clock 1: System clock (φ) is selected as the operating clock.
6.3.3 Wait State Control Register (WSCR) WSCR is used to specify the data bus width, the number of access states, the wait mode, and the number of wait states for access to external address spaces (basic extended area and 256-kbyte extended area). The bus width and the number of access states for internal memory and internal I/O registers are fixed regardless of the WSCR settings.
Bit Bit Name Initial Value R/W 4 AST 1 R/W Description Basic Extended Area Access State Control Selects the number of states for access to the basic extended area. This bit also enables or disables wait-state insertion. [ADMXE = 0] Normal extension 0: 2-state access space. Wait state insertion disabled 1: 3-state access space. Wait state insertion enabled [ADMXE = 1] Address-data multiplex extension 0: 2-state data access space. Wait state insertion disabled 1: 3-state data access space.
6.3.4 Wait State Control Register 2 (WSCR2) WSCR2 is used to specify the wait mode and number of wait states in access to the 256-kbyte extended area and CP extended area. Bit Bit Name Initial Value R/W Description 7 WMS10 0 R/W 256-kbyte Extended Area Wait Mode Select 0 Selects the wait mode for access to the 256-kbyte extended area when the CS256E bit in SYSCR and the AST256 bit in WSCR are set to 1.
• When ADMXE = 0 Bit Bit Name Initial Value R/W Description 2 1 0 WC22 WC21 WC20 1 1 1 R/W R/W R/W CP Extended Area Wait Count 2 to 0 Select the number of program wait states to be inserted for access to the CP extended area when the CPCSE and ASTCP bits in BCR2 are set to 1. If the CP extended area is selected, the WC22 bit must be cleared to 0.
6.4 Bus Control 6.4.1 Bus Specifications The external address space bus specifications consist of three elements: bus width, the number of access states, and the wait mode and the number of program wait states. The bus width and the number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller settings.
Table 6.2 Address Ranges and External Address Spaces Areas Address Range H'080000 to H'F7FFFF Basic Extended Area No condition 256-kbyte Extended Area, CP Extended Area (Basic Mode) (15 Mbytes) H'F80000 to H'FBFFFF (256 kbytes) ∆ When CS256E = 0, used as basic extended area. 256-kbyte extended area H'FC0000 to H'FEFFFF No condition When WAIT pin function is not selected while CS256E = 1, CS256 is output and address pins A17 to A0 are used.
Table 6.
Table 6.4 Bus Specifications for Basic Extended Area/Basic Bus Interface Bus Specifications Number of Program Wait States ABW AST WMS1 WMS0 WC1 WC0 Bus Width Number of Access States 0 0 * * * * 16 2 0 1 0 1 * * 16 3 0 0 0 3 0 Other than WMS1 = 0 and WMS0 = 1 1 1 1 1 0 2 1 3 0 * * * * 8 2 0 1 0 1 * * 8 3 0 0 0 3 0 Other than WMS1 = 0 and WMS0 = 1 1 1 1 0 2 1 3 [Legend] *: Don’t care Rev. 3.
Table 6.5 Bus Specifications for 256-kbyte Extended Area/Basic Bus Interface Bus Specifications ABW256 AST256 WMS10 WC11 WC10 Bus Width Number of Access States 0 0 * * * 16 2 16 1 1 * * 0 0 0 1 1 Number of Program Wait States 0 3 0 3 0 1 1 0 2 1 3 0 * * * 8 2 0 1 1 * * 8 3 0 0 0 0 3 0 1 [Legend] *: Don’t care Rev. 3.
Table 6.6 Bus Specifications for CP Extended Area (Basic Mode)/Basic Bus Interface Bus Specifications ABWCP ASTCP WMS21 WMS20 WC21 WC20 Bus Width Number of Number of Program Access Wait States States 0 0 * * * * 16 2 0 1 0 1 * * 16 3 0 0 0 3 0 Other than WMS21 = 0 and WMS20 = 1 1 1 0 1 * * 0 1 Other than WMS21 = 0 and WMS20 = 1 1 1 0 2 1 3 * 8 * * 8 0 0 * 1 2 0 3 0 3 0 1 1 0 2 1 3 [Legend] *: Don’t care Rev. 3.
(2) In Address-Data Multiplex Extended Mode (a) Bus Width: A bus width of 8 or 16 bits can be selected via the ABW and ABW256 bits in WSCR, and the ABWCP bit in BCR2. (b) Number of Access States: Two or three states can be selected for data access via the AST and AST256 bits in WSCR, and the ASTCP bit in BCR2. When the 2-state access space is designated, wait-state insertion is disabled.
Table 6.7 Address-Data Multiplex Address Spaces Address Range Address-Data Multiplex Area H'080000 to H'F7FFFF No condition O When the WAIT pin function is not selected and CS256E = 1, CS256 is output and address AD15 to AD0 or AD7 to AD0 are used. No condition No condition No condition No condition O When CPCSE = 1, CPCS1 is output, and address pins AD15 to AD0 or AD7 to AD0 are used.
Table 6.8 Bit Settings and Bus Specifications of Basic Bus Interface Area IOSE CS256E CPCSE 1 0 0 IOS Extended Area 0 1 0 0 CP Extended Area ABW, AST, WMS1, WMS0, WC1, WC0 1 1 256-kbyte Extended Area 0 ABWCP, ASTCP, WMS21, WMS20, WC21, WC20 ABW256, AST256, WMS10, WC11, WC10 Same as when CS256E =0 1 1 ABWCP, ASTCP, WMS21, WMS20, WC21, WC20 0 ABW256, AST256, WMS10, WC11, WC10 1 Table 6.
Table 6.11 Bus Specifications for 256-kbyte Extended Area/Multiplex Bus Interface (Address Cycle) AST256 WMS10 WC22 WC11 WC10 Number of Access States 0 2 1 Number of Program Wait States 0 1 Table 6.12 Bus Specifications for 256-kbyte Extended Area/Multiplex Bus Interface (Data Cycle) WMS1 WC1 WC0 Number of Number of Program Wait Access States States 0 — — — 2 0 1 1 — — 3 0 0 0 0 3 0 AST256 1 1 1 0 2 1 3 Table 6.
Table 6.14 Bus Specifications for CP Extended Area/Multiplex Bus Interface (Data Cycle) ASTCP WMS21 WMS20 WC22 WC21 WC20 Number of Number of Program Access Wait States States 0 — — — — — 2 0 1 0 1 — — — 3 0 0 0 3 0 Other than WMS21 = 0 — and WMS20 = 1 1 6.4.2 1 1 0 2 1 3 Advanced Mode The external address space (H'FFF000 to H'FFF7FF) can be accessed by specifying the AS/IOS pin as an I/O strobe pin.
6.4.3 I/O Select Signals The LSI can output I/O select signals (IOS); the signal is driven low when the corresponding external address space is accessed. Figure 6.2 shows an example of IOS signal output timing. Bus cycle T1 T2 T3 φ Address bus External addresses selected by IOS IOS Figure 6.2 IOS Signal Output Timing Enabling or disabling IOS signal output is performed by the IOSE bit in SYSCR. In the extended mode, the IOS pin functions as an AS pin by a reset.
6.5 Bus Interface The normal extended bus interface enables direct connection to ROM and SRAM. For details on selection of the bus specifications for the basic extended area, 256-kbyte extended area, and CP extended area, see tables 6.4 to 6.6. The address-data multiplex extended bus interface enables direct connection to products that supports this bus interface. For details on selection of the bus specifications for the IOS extended area, 256-kbyte extended area, and CP extended area, see tables 6.
(2) 16-Bit Access Space: Figure 6.4 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8/AD15 to AD8) and lower data bus (D7 to D0/AD7 to AD0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword access is executed as two word accesses. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd.
6.5.2 Valid Strobes Table 6.16 shows the data buses used and valid strobes for each access space. In a read, the RD signal is valid for both the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.
6.5.3 Basic Operation Timing in Normal Extended Mode (1) 8-Bit, 2-State Access Space: Figure 6.5 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states cannot be inserted.
(2) 8-Bit, 3-State Access Space: Figure 6.6 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. Wait states can be inserted.
(3) 16-Bit, 2-State Access Space: Figures 6.7 to 6.9 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states cannot be inserted.
Bus cycle T1 T2 φ Address bus IOS (IOSE = 1) CS256 (CS256E = 1) CPCS1 (CPCSE = 1) AS* (IOSE = 0) RD Read D15 to D8 Invalid D7 to D0 Valid HWR High level LWR Write D15 to D8 Undefined D7 to D0 Valid Note: * For external address space access, this signal is not output when the 256-kbyte expansion area is accessed with CS256E = 1 and when the CP expansion area is accessed with CPCSE = 1. Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access) Rev. 3.
Bus cycle T2 T1 φ Address bus IOS (IOSE = 1) CS256 (CS256E = 1) CPCS1 (CPCSE = 1) AS * (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: * For external address space access, this signal is not output when the 256-kbyte expansion area is accessed with CS256E = 1 and when the CP expansion area is accessed with CPCSE = 1. Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access) Rev. 3.
(4) 16-Bit, 3-State Access Space: Figures 6.10 to 6.12 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states can be inserted.
Bus cycle T1 T2 T3 φ Address bus IOS (IOSE = 1) CS256 (CS256E = 1) CPCS1 (CPCSE = 1) AS* (IOSE = 0) RD Read D15 to D8 Invalid D7 to D0 Valid HWR High level LWR Write D15 to D8 Undefined D7 to D0 Valid Note: * For external address space access, this signal is not output when the 256-kbyte expansion area is accessed with CS256E = 1 and when the CP expansion area is accessed with CPCSE = 1. Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access) Rev. 3.
Bus cycle T1 T2 T3 φ Address bus IOS (IOSE = 1) CS256 (CS256E = 1) CPCS1 (CPCSE = 1) AS* (IOSE = 0) RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: * For external address space access, this signal is not output when the 256-kbyte expansion area is accessed with CS256E = 1 and when the CP expansion area is accessed with CPCSE = 1. Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access) Rev. 3.
6.5.4 Basic Operation Timing in Address-Data Multiplex Extended Mode (1) 8-Bit, 2-State Data Access Space: Figures 6.13 and 6.14 show the bus timing for an 8-bit, 2state access space. When an 8-bit access space is accessed, the upper half (AD15 to AD8) of the data bus is used. Wait states cannot be inserted. Write Cycle Read Cycle Address T1 TAW Address Data T2 T3 T4 T1 TAW Data T2 T3 T4 φ CPCS1 CS256 IOS AH RD HWR AD15 to AD8 Data Address Data Address Figure 6.
(2) 8-Bit, 3-State Data Access Space: Figure 6.15 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (AD15 to AD8) of the data bus is used. Wait states can be inserted. Write Cycle Read Cycle Address T1 TAW Data T2 T3 T4 TDSW Data Address T5 T1 TAW T2 T3 T4 TDSW T5 φ CPCS1 CS256 IOS AH RD HWR AD15 to AD8 Address Data Address Data Figure 6.
Write Cycle Read Cycle Address T1 TAW Data T2 T3 Data Address T4 T1 TAW T2 T3 T4 φ CPCS1 CS256 IOS AH RD HWR LWR AD15 to AD8 Address AD7 to AD0 Address Data Data Address Address Figure 6.16 Bus Timing for 16-Bit, 2-State Access Space (1) (Even Byte Access) Write Cycle Read Cycle Data Address T1 T2 T3 Address T4 T1 T2 Data T3 T4 φ CPCS1 CS256 IOS AH RD HWR LWR AD15 to AD8 Address AD7 to AD0 Address Data Address Data Address Figure 6.
Write Cycle Read Cycle Address T1 TAW Data T2 T3 Data Address T4 T1 TAW T2 T3 T4 φ CPCS1 CS256 IOS AH RD HWR LWR AD15 to AD8 Address AD7 to AD0 Address Address Data Data Address Figure 6.18 Bus Timing for 16-Bit, 2-State Access Space (3) (Odd Byte Access) Write Cycle Read Cycle Address T1 T2 Data T3 Address T4 T1 T2 Data T3 T4 φ CK2S CPCS1 CS256 IOS AH RD HWR LWR AD15 to AD8 Address AD7 to AD0 Address Address Data Address Data Figure 6.
Write Cycle Read Cycle Address T1 TAW Address Data T2 T3 T4 T1 TAW Data T2 T3 T4 φ CPCS2 CS256 IOS AH RD HWR LWR AD15 to AD8 Address Data Address Data AD7 to AD0 Address Data Address Data Figure 6.20 Bus Timing for 16-Bit, 2-State Access Space (5) (Word Access) Write Cycle Read Cycle Data Address T1 T2 T3 Address T4 T1 T2 Data T3 T4 φ CPCS1 CP256 IOS AH RD HWR LWR AD15 to AD8 Address Data Address Data AD7 to AD0 Address Data Address Data Figure 6.
(4) 16-Bit, 3-State Data Access Space: Figures 6.22 to 6.24 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (AD15 to AD8) of the data bus is used for even addresses, and the lower half (AD7 to AD0) for odd addresses. Wait states can be inserted.
Write Cycle Read Cycle Address T1 TAW Data T2 T3 T4 TDSW Data Address T5 T1 TAW T2 T3 T4 TDSW T5 φ CPCS1 CS256 IOS AH RD HWR LWR AD15 to AD8 Address Data Address Data AD7 to AD0 Address Data Address Data Figure 6.24 Bus Timing for 16-Bit, 3-State Access Space (3) (Word Access) 6.5.5 Wait Control When accessing the external address space, this LSI can extend the bus cycle by inserting one or more wait states (TW).
(c) Pin Auto-Wait Mode: A specified number of wait states TW are inserted between the T2 state and T3 state when accessing the external address space if the WAIT pin is low at the falling edge of φ in the last T2 state. The number of wait states TW is specified by the settings of the WC1 and WC0 bits (the WC21 and WC20 bits for the CP extended area). Even if the WAIT pin is held low, TW states are inserted only up to the specified number of states.
(2) In Address-Data Multiplex Extended Mode (a) Program Wait Mode: Program wait mode includes address wait and data wait. 256-kbyte extended area and IOS extended area: Zero or one state of address wait TAW is inserted between T1 and T2 states. Zero to three states of data wait TDSW is inserted between T4 and T5 states. CP extended area: Zero or one state of address wait TAW is inserted between T1 and T2 states. Zero to three states of data wait TDSW is inserted between T4 and T5 states.
Write Cycle Read Cycle Data T3 T4 TDSW TDOW TDOW Data T5 T3 T4 TDSW TDOW TDOW φ CPCS1 CS256 IOS WAIT AH RD HWR LWR AD15 to AD8 Data Data AD7 to AD0 Data Data Figure 6.26 Example of Wait State Insertion Timing Rev. 3.
6.6 Burst ROM Interface In this LSI, the external address space can be designated as the burst ROM space by the BRSTRM bit in BCR, and the burst ROM interface enabled. Consecutive burst accesses of a maximum four or eight words can be performed only during CPU instruction fetch. 1 or 2 states can be selected for burst ROM access. 6.6.1 Basic Operation Timing The number of access states in the initial cycle (full access) of the burst ROM interface is determined by the AST bit in WSCR.
Full access T1 T2 Burst access T1 T1 φ Only lower address changes Address bus AS/IOS (IOSE = 0) RD Data bus Read data Read data Read data Figure 6.28 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0) 6.6.2 Wait Control As with the basic bus interface, program wait insertion or pin wait insertion using the WAIT pin is possible in the initial cycle (full access) of the burst ROM interface. For details, see section 6.5.5, Wait Control. Wait states cannot be inserted in a burst cycle.
6.7 Idle Cycle When this LSI accesses the external address space, it can insert a 1-state idle cycle (TI) between bus cycles when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM with a long output floating time, and high-speed memory and I/O interfaces. If an external write occurs after an external read while the ICIS bit is set to 1 in BCR, an idle cycle is inserted at the start of the write cycle. Figure 6.
6.8 Bus Arbitration 6.8.1 Overview The BSC has a bus arbiter that arbitrates bus master operations. There are two bus masters – the CPU and DTC – that perform read/write operations while they have bus mastership. 6.8.2 Operation Each bus master requests the bus mastership by means of a bus mastership request signal.
Section 7 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 7.1 shows a block diagram of the DTC. The DTC's register information is stored in the onchip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1. A 32-bit bus connects the DTC to addresses H'FFEC00 to H'FFEFFF in on-chip RAM (1 kbyte), enabling 32bit/1-state reading and writing of the DTC register information. 7.
Internal address bus CPU interrupt request [Legend] MRA, MRB: CRA, CRB: SAR: DAR: DTCERA to DTCERE: DTVECR: Internal data bus DTC mode register A, B DTC transfer count register A, B DTC source address register DTC destination address register DTC enable registers A to E DTC vector register Figure 7.1 Block Diagram of DTC Rev. 3.
7.2 Register Descriptions The DTC has the following registers. • • • • • • DTC mode register A (MRA) DTC mode register B (MRB) DTC source address register (SAR) DTC destination address register (DAR) DTC transfer count register A (CRA) DTC transfer count register B (CRB) These six registers cannot be directly accessed from the CPU.
7.2.1 DTC Mode Register A (MRA) MRA selects the DTC operating mode. Bit Bit Name 7 6 SM1 SM0 Initial Value R/W Description Undefined — Source Address Mode 1 and 0 These bits specify an SAR operation after a data transfer.
7.2.2 DTC Mode Register B (MRB) MRB selects the DTC operating mode. Bit Bit Name Initial Value R/W Description 7 CHNE Undefined — DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed. For details, see section 7.6.4, Chain Transfer. In data transfer with CHNE set to 1, determination of the end of the specified number of data transfers, clearing of the interrupt source flag, and clearing of DTCER are not performed.
7.2.5 DTC Transfer Count Register A (CRA) CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts; the upper eight bits (CRAH) and the lower 8 bits (CRAL).
Table 7.
Initial Value Bit Bit Name 6 to 0 DTVEC6 to All 0 DTVEC0 R/W R/W Description DTC Software Activation Vectors 6 to 0 These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + (vector number × 2). For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420. When the SWDTE bit is 0, these bits can be written to. 7.2.9 Keyboard Comparator Control Register (KBCOMP) KBCOMP enables or disables the comparator scan function of event counter.
7.2.10 Event Counter Control Register (ECCR) ECCR selects the event counter channels for use and the detection edge. Bit Bit Name Initial Value R/W Description 7 EDSB 0 R/W Event Counter Edge Select Selects the detection edge for the event counter. 0: Counts the rising edges 1: Counts the falling edges 6 to 4 — All 0 R Reserved These bits are always read as 0 and cannot be modified.
7.2.11 Event Counter Status Register (ECS) ECS is a 16-bit register that holds events temporarily. The DTC decides the counter to be incremented according to the state of this register. Reading this register allows the monitoring of events that are not yet counted by the event counter. Access in 8-bit unit is not allowed.
7.3 DTC Event Counter To count events of EVENT 0 to EVENT15 by the DTC event counter function, set DTC as below. Table 7.2 DTC Event Counter Conditions Register Bit Bit Name MRA 7, 6 SM1, SM0 00: SAR is fixed. MRB Description 5, 4 DM1, DM0 00: DAR is fixed.
When the DTC transfer is completed, the ECS flag for transfer is cleared. Table 7.3 Flag Status/Address Code ECS 15 14 13 12 11 10 9 1 1 7.3.
7.3.2 Usage Notes There are following usage notes for this event counter because it uses the DTC. If these usage notes are not permitted in some applications, use functions such as 8-bit timer event count. 1. 2. 3. 7.4 Continuous events that are input from the same pin and out of DTC handling are ignored because the count up is operated by means of the DTC.
7.5 Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM (addresses: H'FFEC00 to H'FFEFFF). Register information should be located at an address that is a multiple of four within the range. The method for locating the register information in address space is shown in figure 7.3. Locate MRA, SAR, MRB, DAR, CRA, and CRB, in that order, from the start address of the register information.
Table 7.
Table 7.4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs (cont) Activation Source Origin IIC_1 LPC Note: * Activation Source Vector Number DTC Vector Address DTCE* Priority IICI1 98 H'04C4 DTCED3 High ERRI 104 H'04D0 DTCEE3 IBFI1 105 H'04D2 DTCEE2 IBFI2 106 H'04D4 DTCEE1 IBFI3 107 H'04D6 DTCEE0 Low DTCE bits with no corresponding interrupt are reserved, and the write value should always be 0. Rev. 3.
7.6 Operation The DTC stores register information in on-chip RAM. When activated, the DTC reads register information in on-chip RAM and transfers data. After the data transfer, the DTC writes updated register information back to on-chip RAM. The pre-storage of register information in memory makes it possible to transfer data over any required number of channels. The transfer mode can be specified as normal, repeat, or block transfer mode.
7.6.1 Normal Mode In normal mode, one activation source transfers one byte or one word of data. Table 7.5 lists the register functions in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number of transfers has been completed, a CPU interrupt can be requested. Table 7.
7.6.2 Repeat Mode In repeat mode, one activation source transfers one byte or one word of data. Table 7.6 lists the register functions in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers has been completed, the initial states of the transfer counter and the address register that is specified as the repeat area is restored, and transfer is repeated.
7.6.3 Block Transfer Mode In block transfer mode, one activation source transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 7.7 lists the register functions in block transfer mode. The block size can be between 1 and 256. When the transfer of one block ends, the initial state of the block size counter and the address register that is specified as the block area is restored.
7.6.4 Chain Transfer Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 7.8 shows the overview of chain transfer operation. When activated, the DTC reads the register information start address stored at the DTC vector address, and then reads the first register information at that start address.
7.6.5 Interrupt Sources An interrupt request is issued to the CPU when the DTC has completed the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and priority level control by the interrupt controller. In the case of software activation, a software-activated data transfer end interrupt (SWDTEND) is generated.
φ DTC activation request DTC request Data transfer Vector read Address Read Write Read Write Transfer information read Transfer information write Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) φ DTC activation request DTC request Data transfer Data transfer Vector read Address Read Read Write Transfer information read Transfer information write Transfer information read Write Transfer information write Figure 7.
Table 7.
7.7 Procedures for Using DTC 7.7.1 Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Set the corresponding bit in DTCER to 1. [4] Set the enable bits for the interrupt sources to be used as the activation sources to 1.
7.8 Examples of Use of the DTC 7.8.1 Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. [1] Set MRA to a fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0).
[5] Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. [6] If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred. [7] After the transfer, an SWDTEND interrupt occurs.
7.9 Usage Notes 7.9.1 Module Stop Mode Setting DTC operation can be enabled or disabled by the module stop control register (MSTPCR). In the initial state, DTC operation is enabled. Access to DTC registers are disabled when module stop mode is set. Note that when the DTC is being activated, module stop mode can not be specified. For details, refer to section 23, Power-Down Modes. 7.9.2 On-Chip RAM MRA, MRB, SAR, DAR, CRA, and CRB are all located in on-chip RAM.
Section 8 I/O Ports Table 8.1 is a summary of the port functions. The pins of each port also function as input/output pins of peripheral modules and interrupt input pins. Each input/output port includes a data direction register (DDR) that controls input/output and a data register (DR) that stores output data. DDR and DR are not provided for an input-only port. Ports 1 to 3, 6, A, and D0 to D5 have built-in input pull-up MOSs.
Table 8.
Table 8.
Table 8.1 Port Functions (cont) Port Description Port 8 General I/O port also functioning as A/D converter external trigger input pin, SCI_0, SCI_1, and SCI_2 clock inputs/outputs, TMR_0, TMR_1, TMR_X, TMR_Y inputs, and IIC_0 and IIC_1 inputs/outputs Port 9 General I/O port also functioning as bus control input/output, system clock output, and external subclock input Extended Mode (EXPE = 1) Single-Chip Mode (EXPE = 0) I/O Status P87/ExIRQ15/ADTRG/ExTMIY NMOS pushpull outputs.
Table 8.
Table 8.1 Port Functions (cont) Extended Mode (EXPE = 1) Port Description Port E General I/O port also PE7/SERIRQ functioning as LPC PE6/LCLK I/O PE5/LRESET PE4/LFRAME PE3/LAD3 PE2/LAD2 PE1/LAD1 PE0/LAD0 General I/O port also PF2/ExPW2 functioning as PWM PF1/ExPW1 output pin PF0/ExPW0 Port F Notes: 1. 8-bit data bus is selected. 2. 16-bit data bus is selected. Rev. 3.
8.1 Port 1 Port 1 is an 8-bit I/O port. Port 1 pins also function as an address bus, PWM output pins, and address/data multiplex bus. Port 1 functions change according to the operating mode. Port 1 has the following registers. • Port 1 data direction register (P1DDR) • Port 1 data register (P1DR) • Port 1 pull-up MOS control register (P1PCR) 8.1.1 Port 1 Data Direction Register (P1DDR) The individual bits of P1DDR specify input or output for the pins of port 1.
8.1.2 Port 1 Data Register (P1DR) P1DR stores output data for the port 1 pins. Bit Bit Name Initial Value R/W Description 7 P17DR 0 R/W 6 P16DR 0 R/W 5 P15DR 0 R/W 4 P14DR 0 R/W 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 P10DR 0 R/W 8.1.3 P1DR stores output data for the port 1 pins that are used as the general output port. If a port 1 read is performed while the P1DDR bits are set to 1, the P1DR values are read.
8.1.4 Pin Functions The relationship between register setting values and pin functions are as follows in each operating mode. Extended Mode (EXPE = 1): The function of port 1 pins is switched as shown below according to the P1nDDR bit.
8.1.5 Port 1 Input Pull-Up MOS Port 1 has a built-in input pull-up MOS that can be controlled by software. This input pull-up MOS can be used regardless of the operating mode. Table 8.2 summarizes the input pull-up MOS states. Table 8.2 Port 1 Input Pull-Up MOS States Reset Hardware Standby Software Standby Mode Mode In Other Operations Off Off On/Off On/Off [Legend] Off: Always off. On/Off: On when P1DDR = 0 and P1PCR = 1; otherwise off. Rev. 3.
8.2 Port 2 Port 2 is an 8-bit I/O port. Port 2 pins also function as an address bus, PWM output pins, and address-data multiplex bus. Port 2 functions change according to the operating mode. Port 2 has the following registers. • Port 2 data direction register (P2DDR) • Port 2 data register (P2DR) • Port 2 pull-up MOS control register (P2PCR) 8.2.1 Port 2 Data Direction Register (P2DDR) The individual bits of P2DDR specify input or output for the pins of port 2.
8.2.2 Port 2 Data Register (P2DR) P2DR stores output data for the port 2 pins. Bit Bit Name Initial Value R/W Description 7 P27DR 0 R/W 6 P26DR 0 R/W P2DR stores output data for the port 2 pins that are used as the general output port. 5 P25DR 0 R/W 4 P24DR 0 R/W 3 P23DR 0 R/W 2 P22DR 0 R/W 1 P21DR 0 R/W 0 P20DR 0 R/W 8.2.3 If a port 2 read is performed while the P2DDR bits are set to 1, the P2DR values are read.
8.2.4 Pin Functions The relationship between register setting values and pin functions are as follows in each operating mode. Extended Mode (EXPE = 1): The function of port 2 pins is switched as shown below according to the combination of the CS256E and IOSE bits in SYSCR, the ADFULLE and CPCSE bits in BCR2 of BSC, and the P2nDDR bit.
P2nDDR 0 ADMXE Pin function 1 0 1 0 1 P2n input pins AD10 to AD8 input/output pins A10 to A8 output pins AD10 to AD8 input/output pins [Legend] n = 7 to 0 Single-Chip Mode (EXPE = 0): The function of port 2 pins is switched as shown below according to the combination of the OEm bit in PWOERB of PWR and the P2nDDR bit. P2nDDR 0 OEm 0 1 P27 to P20 input pins P27 to P20 output pins PW15 to PW8 output pins Pin function 1 [Legend] n = 7 to 0 m = 15 to 8 8.2.
8.3 Port 3 Port 3 is an 8-bit I/O port. Port 3 pins also function as a bidirectional data bus, wake-up event input pins. Port 3 functions change according to the operating mode. Port 3 has the following registers. • Port 3 data direction register (P3DDR) • Port 3 data register (P3DR) • Port 3 pull-up MOS control register (P3PCR) 8.3.1 Port 3 Data Direction Register (P3DDR) The individual bits of P3DDR specify input or output for the pins of port 3.
8.3.3 Port 3 Pull-Up MOS Control Register (P3PCR) P3PCR controls the port 3 built-in input pull-up MOSs. Bit Bit Name Initial Value R/W Description 7 P37PCR 0 R/W In normal extended mode: 6 P36PCR 0 R/W Operation is not affected. 5 P35PCR 0 R/W In other mode: 4 P34PCR 0 3 P33PCR 0 2 P32PCR 0 R/W When the pins are in input state, the corresponding input pull-up MOS is turned on when a P3PCR bit is set R/W to 1. R/W 1 P31PCR 0 R/W 0 P30PCR 0 R/W 8.3.
• P36/WUE14 The pin function is switched as shown below according to the P36DDR bit. When the WUEM14 bit in WUEMR3 of the interrupt controller is cleared to 0, this pin can be used as the WUE14 input pin. To use this pin as the WUE14 input pin, clear the P36DDR bit to 0. P36DDR WUEM14 Pin function 0 1 0 1 WUE14 input pin P36 input pin P36 output pin • P35/WUE13 The pin function is switched as shown below according to the P35DDR bit.
• P32/WUE10 The pin function is switched as shown below according to the P32DDR bits. When the WUEM10 bit in WUEMR3 of the interrupt controller is cleared to 0, this pin can be used as the WUE10 input pin. To use this pin as the WUE10 input pin, clear the P32DDR bit to 0. P32DDR WUEM10 Pin function 0 1 0 1 WUE10 input pin P32 input pin P32 output pin • P31/WUE9 The pin function is switched as shown below according to the P31DDR bits.
8.3.5 Port 3 Input Pull-Up MOS Port 3 has a built-in input pull-up MOS that can be controlled by software. This input pull-up MOS can be used in single-chip mode. Table 8.4 summarizes the input pull-up MOS states. Table 8.
8.4 Port 4 Port 4 is an 8-bit I/O port. Port 4 pins also function as external interrupt input, and TMR_0, TMR_1, TMR_X, and TMR_Y input/output pins. Port 4 has the following registers. • Port 4 data direction register (P4DDR) • Port 4 data register (P4DR) 8.4.1 Port 4 Data Direction Register (P4DDR) The individual bits of P4DDR specify input or output for the pins of port 4.
8.4.3 Pin Functions The relationship between register setting values and pin functions are as follows. • P47/IRQ7/TMOY The pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCSR of TMR_Y and the P47DDR bit. When the ISS7 bit in ISSR is cleared to 0 and the IRQ7E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ7 input pin. To use this pin as the IRQ7 input pin, clear the P47DDR bit to 0.
• P45/IRQ5/TMIY The pin function is switched as shown below according to the P45DDR bit. When the TMIYS bit in PTCNT0 is cleared to 0 and the external clock is selected by the CKS2 to CKS0 bits in TCR of TMR_Y, this bit is used as the TMCIY input pin. When the CCLR1 and CCLR0 bits in TCR of TMR_Y are set to 1, this pin is used as the TMRIY input pin. When the ISS5 bit in ISSR is cleared to 0 and the IRQ5E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ5 input pin.
• P42/IRQ2/TMO0 The pin function is switched as shown below according to the OS3 to OS0 bits in TCSR of TMR_0 and the P42DDR bit. When the ISS2 bit in ISSR is cleared to 0 and the IRQ2E bit in IER of the interrupt controller is set to 1, this pin can be used as the IRQ2 input pin. To use this pin as the IRQ2 input pin, clear the P42DDR bit to 0.
8.5 Port 5 Port 5 is an 8-bit I/O port. Port 5 pins also function as interrupt input pins, the PWMX output pin, SCI_0, SCI_1, and SCI_2 input/output pins. Port 5 has the following registers. • Port 5 data direction register (P5DDR) • Port 5 data register (P5DR) 8.5.1 Port 5 Data Direction Register (P5DDR) The individual bits of P5DDR specify input or output for the pins of port 5.
8.5.3 Pin Functions The relationship between register setting values and pin functions are as follows. • P57/IRQ15/PWX1 The pin function is switched as shown below according to the combination of the OEB bit in DACR of PWMX and the P57DDR bit. When the ISS15 bit in ISSR16 is cleared to 0 and the IRQ15E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ15 input pin. To use this pin as the IRQ15 input pin, clear the P57DDR bit to 0.
• P54/IRQ12/TxD2 The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_2 and the P54DDR bit. When the ISS12 bit in ISSR16 is cleared to 0 and the IRQ12E bit in IER16 of the interrupt controller is set to 1 this pin can be used as the IRQ12 input pin. To use this pin as the IRQ12 input pin, clear the P54DDR bit to 0.
• P51/IRQ9/RxD0 The pin function is switched as shown below according to the combination of the RE bit in SCR of SCI_0 and the P51DDR bit. When the ISS9 bit in ISSR16 is cleared to 0 and the IRQ9E bit in IER16 of the interrupt controller is set to 1, this pin can be used as the IRQ9 input pin. To use this pin as the IRQ9 input pin, clear the P51DDR bit to 0.
8.6 Port 6 Port 6 is an 8-bit I/O port. Port 6 pins also function as the FRT input/output pin, keyboard input pin, and noise cancel input pin. Port 6 functions change according to the operating mode. The port can be used as the extended data bus (lower eight bits). Port 6 has the following registers.
8.6.2 Port 6 Data Register (P6DR) P6DR stores output data for the port 6 pins. Bit Bit Name Initial Value R/W Description 7 P67DR 0 R/W Normal extended mode (16-bit data bus): 6 P66DR 0 R/W 5 P65DR 0 R/W 4 P64DR 0 R/W If a port 6 read is performed while the P6DDR bits are set to 1, the P6DR values are read. If a port 6 read is performed while the P6DDR bits are cleared to 0, 1 is read.
8.6.4 System Control Register 2 (SYSCR2) SYSCR2 controls the current specifications for the port 6 input pull-up MOSs and address data multiplex operation. Bit Bit Name Initial Value R/W Description 7, 6 All 0 R/W Reserved The initial value should not be changed. 5 P6PUE 0 R/W Port 6 Input Pull-Up Extra Selects the current specification for the input pull-up MOS connected by means of KMPCR settings.
8.6.6 Noise Canceler Mode Control Register (P6NCMC) P6NCMC controls whether 1 or 0 is expected for the input signal to port 6 in bit units. Bit Bit Name Initial Value R/W Description 7 P67NCMC 1 R/W In 16 bit bus mode in extended mode: 6 P66NCMC 1 R/W Port 6 operates as the data pin (D7 to D0).
φ/2, φ/32, φ/512, φ/8192, φ/32768, φ/65536, φ/131072, φ/2621446 Sampling clock selection t Latch Latch Latch t Sampling clock Figure 8.1 Noise Canceler Circuit P6n Input 1 expected P6nDR 0 expected P6nDR Figure 8.2 Noise Canceler Operation Rev. 3.
8.6.8 Pin Functions Normal Extended Mode: Port 6 automatically become the bidirectional data bus in 16-bit bus mode. The port 6 pins function the same as in shingle chip mode in 8-bit bus mode. Address-Data Multiplex Extended Mode: The port 6 pins function the same as in shingle chip mode. Single Chip Mode: The relationship between the register setting values and pin functions are as follows. Port 6 pins also function as the FRT input/output pin, keyboard input pin, noise cancel input pin, or I/O port.
• P65/FTID/KIN5 The function of port 6 pins is switched as shown below according to the P65DDR bit. When the ICIDE bit in TIER of FRT is set to 1, this pin can be used as the FTID input pin. When the KMIM5 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be used as the KIN5 input pin. To use this pin as the KIN5 input pin, clear the P65DDR bit to 0.
• P63/FTIB/KIN3 The function of port 6 pins is switched as shown below according to the P63DDR bit. When the ICIBE bit in TIER of FRT is set to 1, this pin can be used as the FTIB input pin. When the KMIM3 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be used as the KIN3 input pin. To use this pin as the KIN3 input pin, clear the P63DDR bit to 0.
• P61/FTOA/KIN1 The function of port 6 pins is switched as shown below according to the combination of the OEA bit in TOCR of FRT, and the P61DDR bit. When the KMIM1 bit in KMIMR6 of the interrupt controller is cleared to 0, this pin can be used as the KIN1 input pin. To use this pin as the KIN1 input pin, clear the P61DDR bit to 0.
8.6.9 Port 6 Input Pull-Up MOS Port 6 has a built-in input pull-up MOS that can be controlled by software. This input pull-up MOS can be used regardless of the operating mode. Table 8.5 summarizes the input pull-up MOS states. Table 8.5 Port 6 Input Pull-Up MOS States Reset Hardware Standby Mode Software Standby Mode In Other Operations Off Off On/Off On/Off [Legend] Off : Always off. On/Off : On when input state and KMPCR = 1; otherwise off. 8.7 Port 7 Port 7 is an 8-bit input port.
8.7.2 Pin Functions Each pin of port 7 can also be used as the interrupt input pins (ExIRQ2 to ExIRQ7), analog input pin of the A/D converter (AN0 to AN7), and analog output pin (DA0, DA1) of the D/A converter. By setting the ISS bit of the ISSR to 1, the pins can also be used as the interrupt input pin (ExIRQ2 to ExIRQ7). When the interrupt input pin is set, do not use the pins for the A/D or D/A converter.
• P75/ExIRQ5/AN5 The port 7 function changes as shown in the following table, depending on the combination of the SCAN bit and the CH2 to CH0 bits of ADCSR of the A/D converter and the ISS5 bit of ISSR of the interrupt controller. Do not set these bits to other values than those shown in the following table.
• P72/ExIRQ2/AN2 The port 7 function changes as shown in the following table, depending on the combination of the SCAN bit and the CH2 to CH0 bits of ADCSR of the A/D converter and the ISS2 bit of ISSR of the interrupt controller. Do not set these bits to other values than those shown in the following table.
8.8 Port 8 Port 8 is an 8-bit I/O port. Port 8 pins also function as the A/D converter external trigger input pin, SCI_0, SCI_1, and SCI_2 clock input/output pins, IIC_0 and IIC_1 input/output pins, TMR_0, TMR_1, TMR_X, and TMR_Y input pins, and interrupt input pins. Port 8 is an NMOS push-pull output. Port 8 has the following registers. • Port 8 data direction register (P8DDR) • Port 8 data register (P8DR) 8.8.
8.8.3 Pin Functions The relationship between register setting values and pin functions are as follows. • P87/ExIRQ15/ADTRG/ExTMIY The pin function is switched as shown below according to the P87DDR bit. When the TRGS1 and TRGS0 bits in ADCR of the A/D converter are both set to 1, this pin can be used as the ADTRG input pin. When the ISS15 bit in ISSR16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ15 input pin.
• P85/ExIRQ13/SCK1/ExTMI1 The pin function is switched as shown below according to the combination of the C/A bit in SMR of SCI_1, the CKE1 and CKE0 bits in SCR, and the P85DDR bit. When the ISS13 bit in ISSR16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ13 input pin. When the TMI1S bit in PTCNT0 is set to 1, this pin can be used as the TMI1 (TMI1/TMRI1) input pin. To use this pin as the ExIRQ13 input pin, clear the P85DDR bit to 0.
• P83/ExIRQ11/SDA1 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_1 and the P83DDR bit. When the ISS11 bit in ISSR16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ11 input pin. To use this pin as the ExIRQ11 input pin, clear the P83DDR bit to 0. When this pin is used as the P83 output pin, the output format is NMOS push-pull output. The output format for SDA1 is NMOS open-drain output, and direct bus drive is possible.
• P80/ExIRQ8/SCL0 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_0 and the P80DDR bit. When the ISS8 bit in ISSR16 of the interrupt controller is set to 1, this pin can be used as the ExIRQ8 input pin. To use this pin as the ExIRQ8 input pin, clear the P80DDR bit to 0. When this pin is used as the P80 output pin, the output format is NMOS push-pull output. The output format for SCL0 is NMOS open-drain output, and direct bus drive is possible.
8.9 Port 9 Port 9 is an 8-bit I/O port. Port 9 pins also function as the bus control I/O pins or the system clock output pin. Pin functions are switched depending on the operating mode. Port 9 has the following registers. • Port 9 data direction register (P9DDR) • Port 9 data register (P9DR) 8.9.1 Port 9 Data Direction Register (P9DDR) The individual bits of P9DDR specify input or output for the pins of port 9.
8.9.2 Port 9 Data Register (P9DR) P9DR stores output data for the port 9 pins. Bit Bit Name Initial Value R/W Description 7 P97DR 0 R/W 6 P96DR Undefined* R P9DR stores output data for the port 9 pins that are used as the general output port except for bit 6. 5 P95DR 0 R/W 4 P94DR 0 R/W 3 P93DR 0 R/W 2 P92DR 0 R/W 1 P91DR 0 R/W 0 P90DR 0 R/W If a port 9 read is performed while the P9DDR bits are set to 1, the P9DR values are read.
• P96/φ/EXCL The pin function is switched as shown below according to the combination of the EXCLE bit in LPWRCR and the P96DDR bit. P96DDR 0 0 1 P96 input pin EXCL input pin φ output pin EXCLE Pin function 1 • P95/AS/IOS The pin function is switched as shown below according to the combination of the operating mode, the IOSE bit in SYSCR, and the P95DDR bit.
• P92/CPCS1 The pin function is switched as shown below according to the combination of the operating mode, the CPCSE bit in BCR2 of BSC, and the P92DDR bit. Operating Mode Extended Mode CPCSE P92DDR Pin function 0 Single-Chip Mode 1 0 1 P92 input pin P92 output pin 0 1 CPCS1 output pin P92 input pin P92 output pin • P91/AH The pin function is switched as shown below according to the combination of the operating mode, the ADMXE bit of SYSCR2, and the P91DDR bit.
8.10 Port A Port A is an 8-bit I/O port. Port A pins also function as the address output, event counter input, keyboard input, and SCI_0 and SCI_2 external control pins. Pin functions are switched depending on the operating mode. Port A has the following registers. PADDR and PAPIN have the same address. • Port A data direction register (PADDR) • Port A output data register (PAODR) • Port A input data register (PAPIN) 8.10.
8.10.2 Port A Output Data Register (PAODR) PAODR stores output data for the port A pins. Bit Bit Name Initial Value R/W Description 7 PA7ODR 0 R/W 6 PA6ODR 0 R/W PAODR stores output data for the port A pins that are used as the general output port. 5 PA5ODR 0 R/W 4 PA4ODR 0 R/W 3 PA3ODR 0 R/W 2 PA2ODR 0 R/W 1 PA1ODR 0 R/W 0 PA0ODR 0 R/W 8.10.3 Port A Input Data Register (PAPIN) PAPIN indicates the pin states.
8.10.4 Pin Functions The relationship between the operating mode, register setting values, and pin functions are as follows. Normal Extended Mode: Port A functions as address output, keyboard input, external control input of SCI_0 and SCI_2, and also as an I/O port, and input or output can be specified in bit units.
SSE 0 1 C/A 1 CEK1 1 PA1DDR 0 Address 13 Pin function 1 0 PA1 output pin A17 output pin SSE2I input pin 1 PA1 input pin 1 KIN9 input pin /EVENT1 input pin • PA0 /KIN8/EVENT0/A16/SSE0I The function of port A pins is switched as shown below according to the combination of the SSE bit in SEMR of SCI_0, the C/A bit in SMR, the CKE1 bit in SCR, address 13 setting, and the PA0DDR bit.
PAnDDR Pin function 0 1 PAn input pins PAn output pins KINm input pin/EVENTn input pins [Legend] n = 7 to 2 m = 15 to 10 • PA1/KIN9/EVENT1/SSE2I The function of port A pins is switched as shown below according to the combination of the SSE bit in SEMR of SCI_2, the C/A bit in SMR, the CKE1 bit in SCR, and the PA1DDR bit. When the KMIM9 bit in KMIMRA of the interrupt controller is cleared to 0, this pin can be used as the KIN9 input pin. To use this pin as the KIN9 input pin, clear the PA1DDR bit to 0.
SSE 0 1 C/A 1 CKE1 1 PA0DDR Pin function 0 1 PA0 input pin PA0 output pin SSE0I KIN8 input pin /EVENT0 input pin 8.10.5 Input Pull-Up MOS Port A has a built-in input pull-up MOS that can be controlled by software. This input pull-up MOS can be used in any operating mode, and can be specified as on or off on a bit-by-bit basis.
8.11 Port B Port B is an 8-bit multi-function input/output port that can also be used event counter input pin. Port B has the following registers. • Port B data direction register (PBDDR) • Port B output data register (PBODR) • Port B input data register (PBPIN) 8.11.1 Port B Data Direction Register (PBDDR) PBDDR is used to specify the input/output attribute of each pin of port B.
8.11.3 Port B Input Data Register (PBPIN) PBPIN indicates the pin states. Bit Bit Name Initial Value R/W Description 7 PB7PIN Undefined* R 6 PB6PIN Undefined* R Pin states can be read by performing a read cycle on this register. 5 PB5PIN Undefined* R 4 PB4PIN Undefined* R 3 PB3PIN Undefined* R 2 PB2PIN Undefined* R 1 PB1PIN Undefined* R 0 PB0PIN Undefined* R This register is assigned to the same address as that of P8DDR.
• PB5/ EVENT13 PB5DDR 0 1 Event counter* Pin function 1 Disable Enable PB5 input pin EVENT13 input pin PB5 output pin • PB4/EVENT12 PB4DDR 0 1 Event counter* Pin function 1 Disable Enable PB4 input pin EVENT12 input pin PB4 output pin • PB3/EVENT11 PB3DDR 0 1 Event counter* Pin function 1 Disable Enable PB3 input pin EVENT11 input pin PB3 output pin Disable Enable PB2 input pin EVENT10 input pin PB2 output pin • PB2/EVENT10 PB2DDR 0 Event counter*1 Pin function
8.12 Port C Port C is an 8-bit multi-function I/O port that functions as PWMX output pins or input/output pins of IIC_2, 3, 4. The output format of ports C0 to C5 is NMOS push-pull output. Port C has the following registers. • Port C data direction register (PCDDR) • Port C output data register (PCODR) • Port C input data register (PCPIN) 8.12.1 Port C Data Direction Register (PCDDR) PCDDR is used to specify the input/output attribute of each pin of port C.
8.12.3 Port C Input Data Register (PCPIN) PCPIN indicates the pin states of port C. Bit 7 6 5 Bit Name PC7PIN PC6 PIN PC5 PIN Initial Value R/W Description 1 R When this register is read, the pin state is read. 1 R 1 R 1 This register is assigned to the same address as that of PCDDR. When this register is written to, data is written to PCDDR and the port C setting is then changed.
• PC5/SDA4 The pin function is switched as shown below according to the combination of the ICE bit of the IIC_4 ICCR and the PC5DDR. ICE PC5DDR Pin Function 0 1 0 1 PC5 input pin PC5 output pin SDA4 input/output pin • PC4/SCL4 The pin function is switched as shown below according to the combination of the ICE bit of the IIC_4 ICCR and the PC4DDR.
• PC0/SCL2 The pin function is switched as shown below according to the combination of the ICE bit of the IIC_2 ICCR and the PC0DDR. ICE 0 0 1 PC0 input pin PC0 output pin SCL2 input/output pin PC0DDR Pin Function 8.13 1 Port D Port D is an 8-bit multi-function I/O port that supports the following register set. Port D functions as both the IIC_5 I/O pin, and the LPC I/O pin. Ports D7 and D6 are NMOS push-pull outputs.
8.13.2 Port D Output Data Register (PDODR) PDODR stores output data for the port D pins. Bit Bit Name Initial Value R/W Description 7 PD7ODR 0 R/W 6 PD6ODR 0 R/W The PDODR register stores the output data for the pins that are used a general output port. 5 PD5ODR 0 R/W 4 PD4ODR 0 R/W 3 PD3ODR 0 R/W 2 PD2ODR 0 R/W 1 PD1ODR 0 R/W 0 PD0ODR 0 R/W 8.13.3 Port D Input Data Register (PDPIN) PDPIN indicates the pin states of port D.
8.13.4 Pin Functions Port D is a multi-function port that functions as an LPC input/output and IIC_5 input/output. The relationship between the register settings and pin functions is described below. The LPC module is disabled when the LPC1E, LPC2E, and LPC3E bits in HICR0 of LPC are all cleared to a 0. • PD7/SDA5 The pin function is switched as shown below according to the combination of the ICE bit of the IIC_5 ICCR and the PD7DDR.
• PD3/GA20 The pin function is switched as shown below according to the combination of the FGA20E bit of LPC HICR0 and the PD3DDR. FGA20E PD3DDR Pin Function 0 1 0 1 0 PD3 input pin PD3 output pin GA20 output pin • PD2/PME The pin function is switched as shown below according to the combination of the PMEE bit of LPC HICR0 and the PD2DDR.
8.13.5 Input Pull-Up MOS Ports D5 to D0 have a built-in input pull-up MOS that can be controlled by software. This input pull-up MOS can be used in any operating mode, and can be specified as on or off on a bit-by-bit basis. PDnDDR 0 1 0 ON OFF OFF PDnODR PDn pull-up MOS 1 [Legend] n = 5 to 0 The input pull-up MOS is in the off state after a reset and in hardware standby mode. The prior state is retained in software standby mode. Table 8.7 summarizes the input pull-up MOS states. Table 8.
8.14 Port E Port E functions as an 8-bit input/output port and also as an LPC input/output. Port E provides the following register set. • Port E data direction register (PEDDR) • Port E output data register (PEODR) • Port E input data register (PEPIN) 8.14.1 Port E Data Direction Register (PEDDR) PEDDR is used to specify the input/output attribute of each pin of port E.
8.14.3 Port E Input Data Register (PEPIN) PEPIN indicates the pin states of port E. Bit Bit Name Initial Value R/W Description 7 PE7PIN Undefined* R 6 PE6PIN Undefined* R Pin states can be read by performing a read cycle on this register. 5 Pe5PIN Undefined* R 4 PE4PIN Undefined* R 3 PE3PIN Undefined* R 2 PE2PIN Undefined* R 1 PE1PIN Undefined* R 0 PE0PIN Undefined* R This register is assigned to the same address as that of PEDDR.
• PE5/LRESET The pin function is switched as shown below according to the LPC enabled/disabled and the PE5DDR. LPC PE5DDR Pin Function Disabled Enabled 0 1 PE5 input pin PE5 output pin LRESET input pin • PE4/LFRAME The pin function is switched as shown below according to the LPC enabled/disabled and the PE4DDR.
• PE0/LAD0 The pin function is switched as shown below according to the LPC enabled/disabled and the PE0DDR. LPC Disabled 0 1 PE0 input pin PE0 output pin LAD0 input/output pin PE0DDR Pin Function 8.15 Enabled Port F Port F is a 3-bit multi-function input/output port supporting the following register set. • Port F data direction register (PFDDR) • Port F output data register (PFODR) • Port F input data register (PFPIN) 8.15.
8.15.3 Port F Input Data Register (PFPIN) PFPIN indicates the pin states of port F. Bit Bit Name Initial Value R/W Description 7 to 3 Reserved. When this bit is read, an undefined value is returned. 2 PF2PIN Undefined* R When PFPIN is read, the pin states are returned. 1 PF1PIN Undefined* R 0 PF0PIN Undefined* R This register is assigned to the same address as that of PFDDR. When this register is written to, data is written to PFDDR and the port F setting is then changed.
8.16 Change of Peripheral Function Pins I/O ports that also function as peripheral modules, such as the external interrupts, 8-bit timer input, and 8-bit PWM timer output, can be changed. I/O ports that also function as the external interrupt pins are changed according to the setting of ISSR16 and ISSR. I/O ports that also function as the 8-bit timer input pins and the 8-bit PWM timer output pins are changed according to the setting of PTCNT0.
• ISSR Bit Bit Name Initial Value R/W Description 7 ISS7 0 R/W 0: P47/IRQ7 is selected 1: P77/ExIRQ7 is selected 6 ISS6 0 R/W 0: P46/IRQ6 is selected 1: P76/ExIRQ6 is selected 5 ISS5 0 R/W 0: P45/IRQ5 is selected 1: P75/ExIRQ5 is selected 4 ISS4 0 R/W 0: P44/IRQ4 is selected 1: P74/ExIRQ4 is selected 3 ISS3 0 R/W 0: P43/IRQ3 is selected 1: P73/ExIRQ3 is selected 2 ISS2 0 R/W 0: P42/IRQ2 is selected 1 ISS1 0 R/W P41/IRQ1 is always selected 0 ISS0 0 R/W P40/IRQ0 is
8.16.2 Port Control Register 0 (PTCNT0) PTCNT0 selects ports that also function as 8-bit timer input pins, and 8-bit PWM timer output pins.
Section 9 8-Bit PWM Timer (PWM) This LSI has an on-chip pulse width modulation (PWM) timer with sixteen outputs. Sixteen output waveforms are generated from a common time base, enabling PWM output with a high carrier frequency to be produced using pulse division. 9.1 Features • Operable at a maximum carrier frequency of 2.
9.2 Input/Output Pins Table 9.1 shows the PWM output pins. Table 9.1 Pin Configuration Name Abbreviation I/O Function PWM output 15 to 0 PW15 to PW0 Output PWM timer pulse output 15 to 0 9.3 Register Descriptions The PWM has the following registers. To access PCSR, the FLSHE bit in the serial timer control register (STCR) must be cleared to 0. For details on the serial timer control register (STCR), see section 3.2.3, Serial Timer Control Register (STCR).
9.3.1 PWM Register Select (PWSL) PWSL is used to select the input clock and the PWM data register. Bit Initial Bit Name Value 7 6 PWCKE PWCKS 0 0 R/W Description R/W PWM Clock Enable PWM Clock Select These bits, together with bits PWCKB and PWCKA in PCSR, select the internal clock input to TCNT in the PWM. For details, see table 9.2. The resolution, PWM conversion period, and carrier frequency depend on the selected internal clock, and can be obtained from the following equations.
Bit Bit Name Initial Value 3 to 0 RS3 to RS0 All 0 R/W Description R/W Register Select These bits select the PWM data register. 0000: PWDR0 selected 0001: PWDR1 selected 0010: PWDR2 selected 0011: PWDR3 selected 0100: PWDR4 selected 0101: PWDR5 selected 0110: PWDR6 selected 0111: PWDR7 selected 1000: PWDR8 selected 1001: PWDR9 selected 1010: PWDR10 selected 1011: PWDR11 selected 1100: PWDR12 selected 1101: PWDR13 selected 1110: PWDR14 selected 1111: PWDR15 selected Table 9.
Table 9.3 Resolution, PWM Conversion Period, and Carrier Frequency when φ = 33 MHz Internal Clock Frequency Resolution PWM Conversion Period Carrier Frequency φ 30 ns 7.76 µs 2063 kHz φ/2 61 ns 15.52 µs 1031 kHz φ/4 121 ns 31.03 µs 515.6 kHz φ/8 242 ns 62.06 µs 257.8 kHz φ/16 485 ns 124.12 µs 128.9 kHz 9.3.2 PWM Data Registers 15 to 0 (PWDR15 to PWDR0) PWDR are 8-bit readable/writable registers. The PWM has sixteen PWM data registers.
• PWDPRB Bit Bit Name Initial Value R/W Description 7 to 0 OS15 to OS8 All 0 R/W Output Select 15 to 8 These bits select the PWM output phase. Bits OS15 to OS8 correspond to outputs PW15 to PW8. 0: PWM direct output (PWDR value corresponds to high width of output) 1: PWM inverted output (PWDR value corresponds to low width of output) 9.3.4 PWM Output Enable Registers A and B (PWOERA and PWOERB) Each PWOER switches between PWM output and port output.
• PWOERB Bit Initial Value R/W Description Bit Name 7 to 0 OE15 to OE8 All 0 R/W Output Enable 15 to 8 These bits, together with P2DDR, specify the P2n/PWm pin state. Bits OE15 to OE8 correspond to outputs PW15 to PW8. P2nDDR OEm: Pin state 0*: Port input 10: Port output or PWM 256/256 output 11: PWM output (0 to 255/256 output) [Legend] n = 0 to 7 m = 8 to 15 *: Don't care To perform PWM 256/256 output when DDR = 1 and OE = 0, the corresponding pin should be set to port output.
9.4 Operation The upper four bits of PWDR specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. Table 9.4 shows the duty cycles of the basic pulse. Table 9.4 Duty Cycle of Basic Pulse Upper 4 Bits Basic Pulse Waveform (Internal) B'0000 H: 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 L: B'0001 B'0010 B'0011 B'0100 B'0101 B'0110 B'0111 B'1000 B'1001 B'1010 B'1011 B'1100 B'1101 B'1110 B'1111 Rev. 3.
The lower four bits of PWDR specify the position of pulses added to the 16 basic pulses. An additional pulse adds a high period (when OS = 0) with a width equal to the resolution before the rising edge of a basic pulse. When the upper four bits of PWDR are B'0000, there is no rising edge of the basic pulse, but the timing for adding pulses is the same. Table 9.5 shows the positions of the additional pulses added to the basic pulses, and figure 9.2 shows an example of additional pulse timing. Table 9.
9.4.1 PWM Setting Example 1-conversion cycle Duty cycle Basic waveform Additiona pulse 7F 127/256 112 pulse 15 pulse 80 128/256 128 pulse 0 pulse 81 129/256 128 pulse 1 pulse 82 130/256 128 pulse 2 pulse PWDR setting example 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 : Pulse added Combination of the basic pulse and added pulse outputs 0/256 to 255/256 of duty cycle as low ripple waveform. Figure 9.3 Example of PWM Setting 9.4.
Section 10 14-Bit PWM Timer (PWMX) This LSI has an on-chip 14-bit pulse-width modulator (PWM) timer with four output channels. It can be connected to an external low-pass filter to operate as a 14-bit D/A converter. 10.1 Features • Division of pulse into multiple base cycles to reduce ripple • Eight resolution settings The resolution can be set to 1, 2, 64, 128, 256, 1024, 4096, or 16384 system clock cycles.
10.2 Input/Output Pins Table 10.1 lists the PWMX (D/A) module input and output pins. Table 10.1 Pin Configuration Name Abbreviation I/O Function PWMX output pin 0 PWX0 Output PWM timer pulse output of PWMX_0 channel A PWMX output pin 1 PWX1 Output PWM timer pulse output of PWMX_0 channel B PWMX output pin 2 PWX2 Output PWM timer pulse output of PWMX_1 channel A PWMX output pin 3 PWX3 Output PWM timer pulse output of PWMX_1 channel B 10.
10.3.1 PWMX (D/A) Counter (DACNT) DACNT is a 14-bit readable/writable up-counter. The input clock is selected by the clock select bit (CKS) in DACR. DACNT functions as the time base for both PWMX (D/A) channels. When a channel operates with 14-bit precision, it uses all DACNT bits. When a channel operates with 12bit precision, it uses the lower 12 bits and ignores the upper two bits. DACNT cannot be accessed in 8-bit units. DACNT should always be accessed in 16-bit units. For details, see section 10.
10.3.2 PWMX (D/A) Data Registers A and B (DADRA and DADRB) DADRA corresponds to PWMX (D/A) channel A, and DADRB to PWMX (D/A) channel B. The DADR registers cannot be accessed in 8-bit units. The DADR registers should always be accessed in 16-bit units. For details, see section 10.4, Bus Master Interface. • DADRA Bit Bit Name 15 to 2 DA13 to DA0 Initial Value R/W Description All 1 R/W D/A Data 13 to 0 These bits set a digital value to be converted to an analog value.
• DADRB Bit Bit Name Initial Value 15 to 2 DA13 to DA0 All 1 R/W Description R/W D/A Data 13 to 0 These bits set a digital value to be converted to an analog value. In each base cycle, the DACNT value is continually compared with the DADR value to determine the duty cycle of the output waveform, and to decide whether to output a fine-adjustment pulse equal in width to the resolution. To enable this operation, this register must be set within a range that depends on the CFS bit.
10.3.3 PWMX (D/A) Control Register (DACR) DACR enables the PWM outputs, and selects the output phase and operating speed. Bit Bit Name Initial Value R/W Description 7 0 R/W Reserved The initial value should not be changed. 6 PWME 0 R/W PWMX Enable Starts or stops the PWM D/A counter (DACNT). 0: DACNT operates as a 14-bit up-counter 1: DACNT halts at H'0003 5, 4 All 1 R Reserved These bits are always read as 1 and cannot be modified.
10.3.4 Peripheral Clock Select Register (PCSR) PCSR and the CKS bit of DACR select the operating speed. Bit Bit Name Initial Value R/W Description 7 6 PWCKX1B PWCKX1A 0 0 R/W R/W PWMX_1 Clock Select These bits select a clock cycle with the CKS bit of DACR of PWMX_1 being 1. See table 10.2. 5 4 PWCKX0B PWCKX0A 0 0 R/W R/W PWMX_0 Clock Select These bits select a clock cycle with the CKS bit of DACR of PWMX_0 being 1. See table 10.2.
10.4 Bus Master Interface DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the on-chip peripheral modules, however, is only 8 bits wide. When the bus master accesses these registers, it therefore uses an 8-bit temporary register (TEMP). These registers are written to and read from as follows. • Write When the upper byte is written to, the upper-byte write data is stored in TEMP.
10.5 Operation A PWM waveform like the one shown in figure 10.2 is output from the PWX pin. DA13 to DA0 in DADR corresponds to the total width (TL) of the low (0) pulses output in one conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 0, this waveform is directly output. When OS = 1, the output waveform is inverted, and DA13 to DA0 in DADR value corresponds to the total width (TH) of the high (1) output pulses. Figures 10.3 and 10.4 show the types of waveform output available.
Table 10.3 Settings and Operation (Examples when φ = 33 MHz) PCSR Fixed DADR Bits ResoConversion TL/TH Accuracy B A CKS (µs) CFS Cycle Cycle (OS = 0/OS = 1) (Bits) 0 0 496.48 Always low/high output 14 C 0.03 1.94 (µs) (µs) /515.6kHz 1 (φ) 0 0 0 1 0.06 7.76 496.48 (µs) (µs) /128.9kHz 0 3.88 (µs) 0.99 (ms) /257.8kHz 1 15.52 (µs) (φ/2) 0 0 1 1 1.94 0.99 (ms) /64.5kHz 0 124.12 (µs) 31.78 (ms) /8.1kHz 1 496.48 (µs) (φ/64) 0 1 0 1 3.88 31.78 (ms) /2.
PCSR Fixed DADR Bits ResoConversion TL/TH Accuracy C B A CKS (µs) CFS Cycle Cycle (OS = 0/OS = 1) (Bits) 0 1 1 1 0 127.10 Always low/high output 14 7.76 496.48 (µs) (ms) /2.0kHz 1 1985.94 (µs) (φ/256) 1 0 0 1 31.03 127.10 (ms) /0.5kHz 0 1.99 (ms) 508.40 (ms) /503.5Hz 1 (φ/1024) 1 0 1 1 124.12 7.94 508.40 (ms) (ms) 7.94 (ms) 2.03 (s) /125.9Hz 1 31.78 (ms) (φ/4096) 1 1 0 1 496.48 2.03 (s) /31.5Hz 0 31.78 (ms) 8.13 (s) /31.5Hz 1 127.
1 conversion cycle tf1 tL1 tf2 tf255 tL2 tL3 tL255 tf256 tL256 tf1 = tf2 = tf3 = ··· = tf255 = tf256 = T× 64 tL1 + tL2 + tL3+ ··· + tL255 + tL256 = TL a. CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle tf1 tL1 tf2 tL2 tf63 tL3 tL63 tf64 tL64 tf1 = tf2 = tf3 = ··· = tf63 = tf64 = T× 256 tL1 + tL2 + tL3 + ··· + tL63 + tL64 = TL b. CFS = 1 [base cycle = resolution (T) × 256] Figure 10.3 Output Waveform (OS = 0, DADR corresponds to TL) Rev. 3.
1 conversion cycle tf1 tH1 tf2 tf255 tH2 tH3 tf256 tH255 tH256 tf1 = tf2 = tf3 = ··· = tf255 = tf256 = T× 64 tH1 + tH2 + tH3 + ··· + tH255 + tH256 = TH a. CFS = 0 [base cycle = resolution (T) × 64] 1 conversion cycle tf1 tH1 tf2 tf63 tH2 tH3 tf64 tH63 tH64 tf1 = tf2 = tf3 = ··· = tf63 = tf64 = T× 256 tH1 + tH2 + tH3 + ··· + tH63 + tH64 = TH b. CFS = 1 [base cycle = resolution (T) × 256] Figure 10.
1 conversion cycle Base cycle No. 0 Base cycle Base cycle No. 1 No. 63 Base pulse High width: 2/256 × (T) Additional pulse output location Base pulse 2/256 × (T) Additional pulse 1/256 × (T) Figure 10.6 Output Waveform when DADR = H'0207 (OS = 1) However, when CFS = 0 (base cycle = resolution (T) × 64), the duty cycle of the base pulse is determined by the upper six bits and the locations of the additional pulses by the subsequent eight bits with a method similar to as above. Rev. 3.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Lower 6 bits 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0
Rev. 3.
Section 11 16-Bit Free-Running Timer (FRT) This LSI has an on-chip 16-bit free-running timer (FRT). The FRT operates on the basis of the 16bit free-running counter (FRC), and outputs two independent waveforms, and measures the input pulse width and external clock periods. 11.1 Features • Selection of four clock sources One of the three internal clocks (φ/2, φ/8, or φ/32), or an external clock input can be selected (enabling use as an external event counter).
Internal clock OCRAR/F φ/2 φ/8 φ/32 Clock Clock selector OCRA Compare-match A Comparator A FTOA Overflow FTOB FRC Clear FTIA FTIB Control logic Compare-match B Comparator B FTIC Bus interface FTCI Module data bus External clock Internal data bus OCRB FTID Input capture ICRA ICRB ICRC ICRD Comparator M ×1 ×2 Compare-match M OCRDM TCSR TIER TCR TOCR ICIA ICIB ICIC ICID OCIA OCIB FOVI Interrupt signal [Legend] OCRA, OCRB: OCRAR,OCRAF: OCRDM: FRC: ICRA to D: TCSR: TIER: TCR: TOCR:
11.2 Input/Output Pins Table 11.1 lists the FRT input and output pins. Table 11.
11.3.1 Free-Running Counter (FRC) FRC is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS1 and CKS0 in TCR. FRC can be cleared by compare-match A. When FRC overflows from H'FFFF to H'0000, the overflow flag bit (OVF) in TCSR is set to 1. FRC should always be accessed in 16-bit units; cannot be accessed in 8-bit units. FRC is initialized to H'0000. 11.3.
11.3.4 Output Compare Registers AR and AF (OCRAR and OCRAF) OCRAR and OCRAF are 16-bit readable/writable registers. When the OCRAMS bit in TOCR is set to 1, the operation of OCRA is changed to include the use of OCRAR and OCRAF. The contents of OCRAR and OCRAF are automatically added alternately to OCRA, and the result is written to OCRA. The write operation is performed on the occurrence of compare-match A. In the 1st compare-match A after setting the OCRAMS bit to 1, OCRAF is added.
11.3.6 Timer Interrupt Enable Register (TIER) TIER enables and disables interrupt requests. Bit Bit Name Initial Value R/W Description 7 ICIAE 0 R/W Input Capture Interrupt A Enable Selects whether to enable input capture interrupt A request (ICIA) when input capture flag A (ICFA) in TCSR is set to 1.
Bit Bit Name Initial Value R/W Description 2 OCIBE 0 R/W Output Compare Interrupt B Enable Selects whether to enable output compare interrupt B request (OCIB) when output compare flag B (OCFB) in TCSR is set to 1. 0: OCIB requested by OCFB is disabled 1: OCIB requested by OCFB is enabled 1 OVIE 0 R/W Timer Overflow Interrupt Enable Selects whether to enable a free-running timer overflow request interrupt (FOVI) when the timer overflow flag (OVF) in TCSR is set to 1.
Bit Bit Name Initial Value R/W Description 6 ICFB 0 R/(W)* Input Capture Flag B This status flag indicates that the FRC value has been transferred to ICRB by means of an input capture signal. When BUFEB = 1, ICFB indicates that the old ICRB value has been moved into ICRD and the new FRC value has been transferred to ICRB.
Bit Bit Name Initial Value R/W Description 3 OCFA 0 R/(W)* Output Compare Flag A This status flag indicates that the FRC value matches the OCRA value. [Setting condition] When FRC = OCRA [Clearing condition] Read OCFA when OCFA = 1, then write 0 to OCFA 2 OCFB 0 R/(W)* Output Compare Flag B This status flag indicates that the FRC value matches the OCRB value.
11.3.8 Timer Control Register (TCR) TCR selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the FRC clock source. Bit Bit Name Initial Value R/W 7 IEDGA 0 R/W Description Input Edge Select A Selects the rising or falling edge of the input capture A signal (FTIA).
Bit Bit Name Initial Value R/W Description 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select 1 and 0 Select clock source for FRC. 00: φ/2 internal clock source 01: φ/8 internal clock source 10: φ/32 internal clock source 11: External clock source (counting at FTCI rising edge) 11.3.
Bit Bit Name Initial Value R/W Description 4 OCRS 0 R/W Output Compare Register Select OCRA and OCRB share the same address. When this address is accessed, the OCRS bit selects which register is accessed. The operation of OCRA or OCRB is not affected. 0: OCRA is selected 1: OCRB is selected 3 OEA 0 R/W Output Enable A Enables or disables output of the output compare A output pin (FTOA).
11.4 Operation 11.4.1 Pulse Output Figure 11.2 shows an example of 50%-duty pulses output with an arbitrary phase difference. When a compare match occurs while the CCLRA bit in TCSR is set to 1, the OLVLA and OLVLB bits are inverted by software. FRC H'FFFF Counter clear OCRA OCRB H'0000 FTOA FTOB Figure 11.2 Example of Pulse Output Rev. 3.
11.5 Operation Timing 11.5.1 FRC Increment Timing Figure 11.3 shows the FRC increment timing with an internal clock source. Figure 11.4 shows the increment timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks (φ). The counter will not increment correctly if the pulse width is shorter than 1.5 system clocks (φ). φ Internal clock FRC input clock FRC N–1 N N+1 Figure 11.
11.5.2 Output Compare Output Timing A compare-match signal occurs at the last state when the FRC and OCR values match (at the timing when the FRC updates the counter value). When a compare-match signal occurs, the level selected by the OLVL bit in TOCR is output at the output compare pin (FTOA or FTOB). Figure 11.5 shows the timing of this operation for compare-match A.
11.5.4 Input Capture Input Timing The rising or falling edge can be selected for the input capture input timing by the IEDGA to IEDGD bits in TCR. Figure 11.7 shows the usual input capture timing when the rising edge is selected. φ Input capture input pin Input capture signal Figure 11.7 Input Capture Input Signal Timing (Usual Case) If ICRA to ICRD are read when the corresponding input capture signal arrives, the internal input capture signal is delayed by one system clock (φ). Figure 11.
11.5.5 Buffered Input Capture Input Timing ICRC and ICRD can operate as buffers for ICRA and ICRB, respectively. Figure 11.9 shows how input capture operates when ICRC is used as ICRA's buffer register (BUFEA = 1) and IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA. φ FTIA Input capture signal FRC n n+1 N N+1 ICRA M n n N ICRC m M M n Figure 11.
CPU read cycle of ICRA or ICRC T1 T2 φ FTIA Input capture signal Figure 11.10 Buffered Input Capture Timing (BUFEA = 1) 11.5.6 Timing of Input Capture Flag (ICF) Setting The input capture flag, ICFA to ICFD, is set to 1 by the input capture signal. The FRC value is simultaneously transferred to the corresponding input capture register (ICRA to ICRD). Figure 11.11 shows the timing of setting the ICFA to ICFD flag. φ Input capture signal ICFA to ICFD FRC N ICRA to ICRD N Figure 11.
11.5.7 Timing of Output Compare Flag (OCF) setting The output compare flag, OCFA or OCFB, is set to 1 by a compare-match signal generated when the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last state in which the two values match, just before FRC increments to a new value. When the FRC and OCRA or OCRB value match, the compare-match signal is not generated until the next cycle of the clock source. Figure 11.12 shows the timing of setting the OCFA or OCFB flag.
11.5.9 Automatic Addition Timing When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are automatically added to OCRA alternately, and when an OCRA compare-match occurs a write to OCRA is performed. Figure 11.14 shows the OCRA write timing. φ FRC N N +1 OCRA N N+A OCRAR, OCRAF A Compare-match signal Figure 11.14 OCRA Automatic Addition Timing 11.5.
φ FRC N ICRD + OCRDM × 2 N+1 N Compare-match signal Input capture mask signal Figure 11.16 Timing of Input Capture Mask Signal Clearing Rev. 3.
11.6 Interrupt Sources The free-running timer can request seven interrupts: ICIA to ICID, OCIA, OCIB, and FOVI. Each interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the interrupt controller for each interrupt. Table 11.2 lists the sources and priorities of these interrupts. The ICIA, ICIB, OCIA, and OCIB interrupts can be used as the on-chip DTC activation sources. Table 11.
11.7 Usage Notes 11.7.1 Conflict between FRC Write and Clear If an internal counter clear signal is generated during the state after an FRC write cycle, the clear signal takes priority and the write is not performed. Figure 11.17 shows the timing for this type of conflict. Write cycle of FRC T1 T2 φ Address FRC address Internal write signal Counter clear signal FRC N H'0000 Figure 11.17 Conflict between FRC Write and Clear Rev. 3.
11.7.2 Conflict between FRC Write and Increment If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes priority and FRC is not incremented. Figure 11.18 shows the timing for this type of conflict. Write cycle of FRC T1 T2 φ Address FRC address Internal write signal FRC input clock FRC N M Write data Figure 11.18 Conflict between FRC Write and Increment Rev. 3.
11.7.3 Conflict between OCR Write and Compare-Match If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes priority and the compare-match signal is disabled. Figure 11.19 shows the timing for this type of conflict. If automatic addition of OCRAR and OCRAF to OCRA is selected, and a compare-match occurs in the cycle following the OCRA, OCRAR, and OCRAF write cycle, the OCRA, OCRAR and OCRAF write takes priority and the compare-match signal is disabled.
φ Address OCRAR (OCRAF) address Internal write signal OCRAR (OCRAF) Compare-match signal Old data New data Disabled FRC N OCR N N+1 Automatic addition is not performed because compare-match signals are disabled. Figure 11.20 Conflict between OCR Write and Compare-Match (When Automatic Addition Function is Used) 11.7.4 Switching of Internal Clock and FRC Operation When the internal clock is changed, the changeover may source FRC to increment.
Table 11.3 Switching of Internal Clock and FRC Operation No. 1 Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from low to low FRC Operation Clock before switchover Clock after switchover FRC clock FRC N N+1 CKS bit rewrite 2 Switching from low to high Clock before switchover Clock after switchover FRC clock FRC N N+1 N+2 CKS bit rewrite 3 Switching from high to low Clock before switchover Clock after switchover * FRC clock FRC N N+1 N+2 CKS bit rewrite Rev. 3.
Table 11.3 Switching of Internal Clock and FRC Operation (cont) No. 4 Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from high to high FRC Operation Clock before switchover Clock after switchover FRC clock FRC N N+1 N+2 CKS bit rewrite Note: * Generated on the assumption that the switchover is a falling edge; FRC is incremented. Rev. 3.
Section 12 8-Bit Timer (TMR) This LSI has an on-chip 8-bit timer module (TMR_0 and TMR_1) with two channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers. This LSI also has a similar on-chip 8-bit timer module (TMR_Y and TMR_X) with two channels. 12.
External clock TMCI0 TMCI1 Internal clock TMR_0 φ/2, φ/8, φ/32, φ/64, φ/256, φ/1024 TMR_1 φ/2, φ/8, φ/64, φ/128, φ/1024, φ/2048 Clock 1 Clock 0 Compare match A1 Compare match A0 Overflow 1 Overflow 0 TMO0 TMRI0 TCORA_0 TCORA_1 Comparator A_0 Comparator A_1 TCNT_0 TCNT_1 Clear 0 Clear 1 Control logic TMO1 TMRI1 Compare match B1 Compare match B0 Comparator B_0 Comparator B_1 TCORB_0 TCORB_1 TCSR_0 TCSR_1 TCR_0 TCR_1 Interrupt signals CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 [Legend] TCORA_0
External clock TMCIY Internal clock TMR_X φ, φ/2, φ/4 TMCIX TMR_Y φ/4, φ/256, φ/2048 Clock X Clock Y Select clock Compare match AX Compare match AY Overflow X Overflow Y TCORA_Y TCORA1_X Comparator A_Y Comparator A_X TCNT_Y TCNT_X Clear Y Compare match BX Compare match BY TMOY TMRIY Control logic TMOX TMRIX Comparator B_Y Comparator B_X TCORB_Y TCORB_X Input capture Internal bus Clear X TICRR TICRF TICR Compare match C Comparator C TCORC TCOR_Y TCSR_X TCR_Y TCR_X TISR Interrup
12.2 Input/Output Pins Table 12.1 summarizes the input and output pins of the TMR. Table 12.
12.3 Register Descriptions The TMR has the following registers for each channel. For details on the serial timer control register, see section 3.2.3, Serial Timer Control Register (STCR).
12.3.2 Time Constant Register A (TCORA) TCORA is an 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit register, so they can be accessed together by word access. TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding compare-match flag A (CMFA) in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORA write cycle.
12.3.4 Timer Control Register (TCR) TCR selects the TCNT clock source and the condition by which TCNT is cleared, and enables/disables interrupt requests. TCR_Y can be accessed when the KINWUE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS is 1. TCR_X can be accessed when the KINWUE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS is 0. See section 3.2.2, System Control Register (SYSCR), and section 12.3.11, Timer Connection Register S (TCONRS).
Table 12.
Table 12.
12.3.5 Timer Control/Status Register (TCSR) TCSR indicates the status flags and controls compare-match output. About the TCSR_Y and TCSR_X accesses see section 3.2.2, System Control Register (SYSCR).
Bit Bit Name Initial Value R/W Description 1 0 OS1 OS0 Output Select 1 and 0 0 0 R/W R/W These bits specify how the TMO0 pin output level is to be changed by compare-match A of TCORA_0 and TCNT_0. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note: * Only 0 can be written, for flag clearing.
Bit Bit Name Initial Value R/W Description 3 2 OS3 OS2 Output Select 3 and 2 0 0 R/W R/W These bits specify how the TMO1 pin output level is to be changed by compare-match B of TCORB_1 and TCNT_1. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) 1 0 OS1 OS0 0 0 R/W R/W Output Select 1 and 0 These bits specify how the TMO1 pin output level is to be changed by compare-match A of TCORA_1 and TCNT_1.
Bit Bit Name Initial Value R/W 5 OVF 0 Description R/(W)* Timer Overflow Flag [Setting condition] When TCNT_Y overflows from H'FF to H'00 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 4 ICIE 0 R/W Input Capture Interrupt Enable [Setting condition] Enables or disables the ICF interrupt request (ICIX) when the ICF bit in TCSR_X is set to 1.
• TCSR_X This register can be accessed when the KINWUE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS is 0.
Bit Bit Name Initial Value R/W Description 1 0 OS1 OS0 Output Select 1 and 0 0 0 R/W R/W These bits specify how the TMOX pin output level is to be changed by compare-match A of TCORA_X and TCNT_X. 00: No change 01: 0 is output 10: 1 is output 11: Output is inverted (toggle output) Note: 12.3.6 * Only 0 can be written, for flag clearing. Input Capture Register (TICR) TICR is an 8-bit register. The contents of TCNT are transferred to TICR at the rising edge of the external reset input.
12.3.9 Timer Input Select Register (TISR) TISR selects a signal source of external clock/reset input for the counter. Bit Bit Name Initial Value R/W Description 7 to 1 Reserved All 1 R/W The initial values should not be modified. 0 IS 0 R/W Input Select Selects TMIY or ExTMIY as the signal source of external clock/reset input for the TMR_Y counter.
12.3.11 Timer Connection Register S (TCONRS) TCONRS selects whether to access TMR_X or TMR_Y registers. Bit Bit Name Initial Value R/W Description 7 TMRX/Y 0 R/W TMR_X/TMR_Y Access Select For details, see table 12.3. 0: The TMR_X registers are accessed at addresses H'FFFFF0 to H'FFFFF5 1: The TMR_Y registers are accessed at addresses H'FFFFF0 to H'FFFFF5 6 to 0 All 0 R/W Reserved The initial values should not be modified. Table 12.
12.4 Operation 12.4.1 Pulse Output Figure 12.3 shows an example for outputting an arbitrary duty pulse. 1. Clear the CCLR1 bit to 0 and set the CCLR0 bit to 1in TCR so that TCNT is cleared according to the compare match of TCORA. 2. Set the OS3 to OS0 bits in TCSR to B'0110 so that 1 is output according to the compare match of TCORA and 0 is output according to the compare match of TCORB.
12.5 Operation Timing 12.5.1 TCNT Count Timing Figure 12.4 shows the TCNT count timing with an internal clock source. Figure 12.5 shows the TCNT count timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks (φ) for a single edge and at least 2.5 system clocks (φ) for both edges. The counter will not increment correctly if the pulse width is less than these values. φ Internal clock TCNT input clock TCNT N–1 N N+1 Figure 12.
φ TCNT N TCOR N N+1 Compare-match signal CMF Figure 12.6 Timing of CMF Setting at Compare-Match 12.5.3 Timing of Timer Output at Compare-Match When a compare-match signal occurs, the timer output changes as specified by the OS3 to OS0 bits in TCSR. Figure 12.7 shows the timing of timer output when the output is set to toggle by a compare-match A signal. φ Compare-match A signal Timer output pin Figure 12.7 Timing of Toggled Timer Output by Compare-Match A Signal 12.5.
12.5.5 TCNT External Reset Timing TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure 12.9 shows the timing of clearing the counter by an external reset input. φ External reset input pin Clear signal TCNT N–1 N H'00 Figure 12.9 Timing of Counter Clear by External Reset Input 12.5.
12.6 TMR_0 and TMR_1 Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, 16-bit count mode or compare-match count mode can be selected. 12.6.1 16-Bit Count Mode When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer with TMR_0 occupying the upper eight bits and TMR_1 occupying the lower eight bits.
12.7 Input Capture Operation TMR_X has input capture registers (TICR, TICRR and TICRF). A narrow pulse width can be measured with TICRR and TICRF, using a single capture. If the falling edge of TMRIX (TMR_X input capture input signal) is detected after its rising edge has been detected, the value of TCNT_X at that time is transferred to both TICRR and TICRF. Input Capture Signal Input Timing: Figure 12.11 shows the timing of the input capture operation.
TICRR, TICRF read cycle T1 T2 φ TMRIX Input capture signal Figure 12.12 Timing of Input Capture Signal (Input capture signal is input during TICRR and TICRF read) Selection of Input Capture Signal Input: TMRIX (input capture input signal of TMR_X) is switched according to the setting of the ICST bits in TCONR1. Input capture signal selections are shown in table 12.4. Table 12.
12.8 Interrupt Sources TMR_0, TMR_1, and TMR_Y can generate three types of interrupts: CMIA, CMIB, and OVI. TMR_X can generate four types of interrupts: CMIA, CMIB, OVI, and ICIX. Table 12.5 shows the interrupt sources and priorities. Each interrupt source can be enabled or disabled independently by interrupt enable bits in TCR or TCSR. Independent signals are sent to the interrupt controller for each interrupt. The CMIA and CMIB interrupts can be used as DTC activation interrupt sources. Table 12.
12.9 Usage Notes 12.9.1 Conflict between TCNT Write and Counter Clear If a counter clear signal is generated during the T2 state of a TCNT write cycle as shown in figure 12.13, the counter clear takes priority and the write is not performed. TCNT write cycle by CPU T1 T2 φ Address TCNT address Internal write signal Counter clear signal TCNT N H'00 Figure 12.13 Conflict between TCNT Write and Counter Clear Rev. 3.
12.9.2 Conflict between TCNT Write and Increment If a TCNT input clock is generated during the T2 state of a TCNT write cycle as shown in figure 12.14, the write takes priority and the counter is not incremented. TCNT write cycle by CPU T1 T2 φ Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 12.14 Conflict between TCNT Write and Increment Rev. 3.
12.9.3 Conflict between TCOR Write and Compare-Match If a compare-match occurs during the T2 state of a TCOR write cycle as shown in figure 12.15, the TCOR write takes priority and the compare-match signal is disabled. With TMR_X, a TICR input capture conflicts with a compare-match in the same way as with a write to TCORC. In this case also, the input capture takes priority and the compare-match signal is disabled.
12.9.4 Conflict between Compare-Matches A and B If compare-matches A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output states set for compare-match A and compare-match B, as shown in table 12.6. Table 12.6 Timer Output Priorities Output Setting Priority Toggle output High 1 output 0 output No change 12.9.5 Low Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 12.
Table 12.7 Switching of Internal Clocks and TCNT Operation (cont) No.
12.9.6 Mode Setting with Cascaded Connection If the 16-bit count mode and compare-match count mode are set simultaneously, the input clock pulses for TCNT_0 and TCNT_1 are not generated, and thus the counters will stop operating. Simultaneous setting of these two modes should therefore be avoided. Rev. 3.
Rev. 3.
Section 13 Watchdog Timer (WDT) This LSI incorporates two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer can output an overflow signal (RESO) externally if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. Simultaneously, it can generate an internal reset signal or an internal NMI interrupt signal. When this watchdog function is not needed, the WDT can be used as an interval timer.
Internal NMI (Interrupt request signal*2) Interrupt control Overflow Clock Clock selection Reset control RESO signal*1 Internal reset signal*1 TCNT_0 φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Internal clock Internal bus WOVI0 (Interrupt request signal) TCSR_0 Bus interface Module bus WDT_0 Internal NMI (Interrupt request signal*2) RESO signal*1 Interrupt control Overflow Clock Clock selection Reset control Internal reset signal*1 φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/1
13.2 Input/Output Pins The WDT has the pins listed in table 13.1. Table 13.1 Pin Configuration Name Symbol I/O Function Reset output pin RESO Output Outputs the counter overflow signal in watchdog timer mode Input Inputs the clock pulses to the WDT_1 prescaler counter External sub-clock input EXCL pin Rev. 3.
13.3 Register Descriptions The WDT has the following registers. To prevent accidental overwriting, TCSR and TCNT have to be written to in a method different from normal registers. For details, see section 13.6.1, Notes on Register Access. For details on the system control register, see section 3.2.2, System Control Register (SYSCR). • Timer counter (TCNT) • Timer control/status register (TCSR) 13.3.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter.
Bit Bit Name Initial Value R/W Description 5 TME Timer Enable 0 R/W When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. 4 0 R/W Reserved The initial value should not be changed. 3 RST/NMI 0 R/W Reset or NMI Selects to request an internal reset or an NMI interrupt when TCNT has overflowed.
• TCSR_1 Bit 7 Bit Name Initial Value R/W OVF 0 Description 1 R/(W)* Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting conditions] • When TCNT overflows (changes from H'FF to H'00) • When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset.
Bit Bit Name Initial Value R/W 2 to 0 CKS2 to CKS0 All 0 R/W Description Clock Select 2 to 0 Select the clock source to be input to TCNT. The overflow cycle for φ = 33 MHz and φSUB = 32.768 kHz is enclosed in parentheses. When PSS = 0: 000: φ/2 (frequency: 15.5 µs) 001: φ/64 (frequency: 496.5 µs) 010: φ/128 (frequency: 993.0 µs) 011: φ/512 (frequency: 4.0 ms) 100: φ/2048 (frequency: 15.9 ms) 101: φ/8192 (frequency: 63.6 ms) 110: φ/32768 (frequency: 254.2 ms) 111: φ/131072 (frequency: 1.
13.4 Operation 13.4.1 Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT bit and the TME bit in TCSR to 1. While the WDT is used as a watchdog timer, if TCNT overflows without being rewritten because of a system malfunction or another error, an internal reset or NMI interrupt request is generated. TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs.
13.4.2 Interval Timer Mode When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows, as shown in figure 13.3. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the same time the OVF bit of TCSR is set to 1. The timing is shown figure 13.4.
RESO Signal Output Timing 13.4.3 When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the RST/NMI bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time, the low level signal is output from the RESO pin. The timing is shown in figure 13.5. φ TCNT H'FF H'00 Overflow signal (internal signal) OVF RESO signal 132 states 518 states Internal reset signal Figure 13.5 Output Timing of RESO signal Rev. 3.
13.5 Interrupt Sources During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. When the NMI interrupt request is selected in watchdog timer mode, an NMI interrupt request is generated by an overflow Table 13.
13.6 Usage Notes 13.6.1 Notes on Register Access The watchdog timer’s registers, TCNT and TCSR differ from other registers in being more difficult to write to. The procedures for writing to and reading from these registers are given below. Writing to TCNT and TCSR (Example of WDT_0): These registers must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. TCNT and TCSR both have the same write address.
13.6.2 Conflict between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 13.7 shows this operation. TCNT write cycle T1 T2 φ Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 13.7 Conflict between TCNT Write and Increment 13.6.
13.6.5 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from/to watchdog timer to/from interval timer, while the WDT is operating, errors could occur in the operation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. 13.6.
Section 14 Serial Communication Interface (SCI, IrDA, and CRC) This LSI has three independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clock synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
Asynchronous Mode: • • • • • Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, overrun, and framing errors Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error • Average transfer rate generator (SCI_0 and SCI_2): 460.606 kbps or 115.152 kbps selectable at 10.667-MHz operation; 720 kbps, 460.784 kbps, 230.392 kbps, or 115.196 kbps selectable at 16- or 24-MHz operation; 230.392 kbps or 115.
RDR TDR BRR SCMR SSR φ SCR RxD1 RSR TSR Baud rate generator SMR φ/4 φ/16 Transmission/ reception control TxD1 Parity generation Internal data bus Bus interface Module data bus φ/64 Clock Parity check External clock SCK1 [Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register TEI TXI RXI ERI SCR: SSR: SCMR: BRR: Serial control register Serial status register Smart card mode register Bit rate regis
RDR TDR SCMR Internal data bus Bus interface Module data bus BRR SSR φ SCR RxD0/ RxD2 RSR TSR Baud rate generator SMR SEMR TxD0/ TxD2 φ/4 φ/16 φ/64 Transmission/ reception control Parity generation Parity check SSE0I/ SSE2I Clock TEI TXI RXI ERI C/A CKE1 Average transfer rate generator SSE External clock SCK0/ SCK2 [Legend] RSR: RDR: TSR: TDR: SMR: Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register SCR: SSR: SCMR: BRR: SE
14.2 Input/Output Pins Table 14.1 shows the input/output pins for each SCI channel. Table 14.
14.3 Register Descriptions The SCI has the following registers for each channel. Some bits in the serial mode register (SMR), serial status register (SSR), and serial control register (SCR) have different functions in different modesnormal serial communication interface mode and smart card interface mode; therefore, the bits are described separately for each mode in the corresponding register sections. . The SCI registers are allocated to the same address.
14.3.3 Transmit Data Register (TDR) TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR when one frame of data is transmitted, the SCI transfers the written data to TSR to continue transmission.
• Bit Functions in Normal Serial Communication Interface Mode (when SMIF in SCMR = 0) Bit Bit Name Initial Value R/W Description 7 C/A 0 R/W Communication Mode 0: Asynchronous mode 1: Clock synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB of TDR is not transmitted in transmission. In clock synchronous mode, a fixed data length of 8 bits is used.
Bit Bit Name Initial Value R/W Description 1 0 CKS1 CKS0 0 0 R/W Clock Select 1 and 0 R/W These bits select the clock source for the baud rate generator. 00: φ clock (n = 0) 01: φ/4 clock (n = 1) 10: φ/16 clock (n = 2) 11: φ/64 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 14.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 14.3.9, Bit Rate Register (BRR)).
Bit Bit Name Initial Value R/W Description 3 2 BCP1 BCP0 0 0 R/W Basic Clock Pulse 1 and 0 R/W These bits select the number of basic clock cycles in a 1-bit data transfer time in smart card interface mode. 00: 32 clock cycles (S = 32) 01: 64 clock cycles (S = 64) 10: 372 clock cycles (S = 372) 11: 256 clock cycles (S = 256) For details, see section 14.7.4, Receive Data Sampling Timing and Reception Margin. S is described in section 14.3.9, Bit Rate Register (BRR).
14.3.6 Serial Control Register (SCR) SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer clock source. For details on interrupt requests, see section 14.9, Interrupt Sources. Some bits in SCR have different functions in normal mode and smart card interface mode.
Bit Bit Name Initial Value R/W Description 1 0 CKE1 CKE0 0 0 R/W Clock Enable 1 and 0 R/W These bits select the clock source and SCK pin function. Asynchronous mode: 00: Internal clock (SCK pin functions as I/O port.) 01: Internal clock (Outputs a clock of the same frequency as the bit rate from the SCK pin.) 1*: External clock (Inputs a clock with a frequency 16 times the bit rate from the SCK pin.) Clock synchronous mode: 0*: Internal clock (SCK pin functions as clock output.
• Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1) Bit Bit Name Initial Value R/W Description 7 TIE 0 R/W Transmit Interrupt Enable When this bit is set to 1,a TXI interrupt request is enabled. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 TE 0 R/W Transmit Enable When this bit is set to 1, transmission is enabled. 4 RE 0 R/W Receive Enable When this bit is set to 1, reception is enabled.
14.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in normal mode and smart card interface mode. • Bit Functions in Normal Serial Communication Interface Mode (when SMIF in SCMR = 0) Bit Bit Name Initial Value R/W Description 7 TDRE 1 R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data.
Bit Bit Name Initial Value R/W Description 5 ORER 0 R/(W)* Overrun Error [Setting condition] When the next serial reception is completed while RDRF = 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 4 FER 0 R/(W)* Framing Error [Setting condition] When the stop bit is 0 [Clearing condition] When 0 is written to FER after reading FER = 1 In 2-stop-bit mode, only the first stop bit is checked.
• Bit Functions in Smart Card Interface Mode (when SMIF in SCMR = 1) Bit Bit Name Initial Value R/W Description 7 TDRE 1 R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR, and TDR can be written to.
Bit 3 Bit Name PER Initial Value 0 R/W Description 1 R/(W)* Parity Error [Setting condition] When a parity error is detected during reception [Clearing condition] When 0 is written to PER after reading PER = 1 2 TEND 1 R Transmit End TEND is set to 1 when the receiving end acknowledges no error signal and the next transmit data is ready to be transferred to TDR.
14.3.8 Smart Card Mode Register (SCMR) SCMR selects smart card interface mode and its format. Bit Bit Name Initial Value R/W Description 7 to 4 All 1 R Reserved These bits are always read as 1 and cannot be modified. 3 SDIR 0 R/W Smart Card Data Transfer Direction Selects the serial/parallel conversion format. 0: TDR contents are transmitted with LSB-first. Stores receive data as LSB first in RDR. 1: TDR contents are transmitted with MSB-first. Stores receive data as MSB first in RDR.
14.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 14.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clock synchronous mode, and smart card interface mode. The initial value of BRR is H′FF, and it can be read from or written to by the CPU at all times. Table 14.
Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency φ (MHz) 5 6 6.144 Bit Rate (bit/s) n N Error (%) n N Error (%) n N 110 2 88 –0.25 2 106 –0.44 2 150 2 64 0.16 2 77 0.16 300 1 129 0.16 1 600 1 64 0.16 1200 0 129 0.16 2400 0 64 4800 0 9600 7.3728 Error (%) 8 n N Error (%) n N 108 0.08 2 130 –0.07 2 141 0.03 2 79 0.00 2 95 0.00 2 103 0.16 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 1 77 0.
Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency φ (MHz) 14 14.7456 16 17.2032 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 248 –0.17 3 64 0.70 3 70 0.03 3 75 0.48 150 2 181 0.16 2 191 0.00 2 207 0.16 2 223 0.00 300 2 90 0.16 2 95 0.00 2 103 0.16 2 111 0.00 600 1 181 0.16 1 191 0.00 1 207 0.16 1 223 0.00 1200 1 90 0.16 1 95 0.00 1 103 0.
Table 14.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) Maximum Bit Rate (bit/s) n N 5 156250 0 0 φ (MHz) Maximum Bit Rate (bit/s) n N 14 437500 0 0 6 187500 0 0 14.7456 460800 0 0 6.144 192000 0 0 16 500000 0 0 7.3728 230400 0 0 17.2032 537600 0 0 8 250000 0 0 18 562500 0 0 9.8304 307200 0 0 19.6608 614400 0 0 10 312500 0 0 20 625000 0 0 12 375000 0 0 25 781250 0 0 12.288 384000 0 0 33 1031250 0 0 Table 14.
Table 14.6 BRR Settings for Various Bit Rates (Clock Synchronous Mode) Operating Frequency φ (MHz) Bit Rate (bit/s) 8 10 16 n N n N n N 250 3 124 3 249 500 2 249 3 1k 2 124 2.
Table 14.8 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, s = 372) Operating Frequency φ (MHz) Bit Rate 7.1424 10.00 13.00 14.2848 16.00 (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 9600 0 0 0.00 0 1 30 0 1 -8.99 0 1 0.00 0 1 12.01 Operating Frequency φ (MHz) Bit Rate 18.00 20.00 21.4272 25 33 (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 9600 0 2 -15.99 0 2 -6.65 0 2 0.
14.3.10 Serial Interface Control Register (SCICR) SCICR controls IrDA operation of SCI_1. Bit Bit Name Initial Value R/W Description 7 IrE 0 R/W IrDA Enable Specifies SCI_1 I/O pins for either normal SCI or IrDA.
14.3.11 Serial Enhanced Mode Register_0 and 2 (SEMR_0 and SEMR_2) SEMR_0 and SEMR_2 select the SCI_0 and SCI_2 functions, respectively, and the clock source in asynchronous mode. The basic clock is automatically specified when the average transfer rate operation is selected. Bit Bit Name Initial Value R/W Description 7 SSE 0 R/W SCI Select Enable Enables/disables the external pins to select the SCI functions when the external clock is supplied in clock synchronous mode.
Bit Bit Name Initial Value R/W Description 4 2 1 0 ACS4 ACS2 ACS1 ACS0 0 0 0 0 R/W R/W R/W R/W Asynchronous Mode Clock Source Select Specify the clock source and the average transfer rate in asynchronous mode. These bits are valid only when external clock is supplied in asynchronous mode.
Bit Bit Name Initial Value R/W Description 4 2 1 0 ACS4 ACS2 ACS1 ACS0 0 0 0 0 R/W 1010: Average transfer rate operation at 115.196 kbps R/W when the system clock frequency is 20 MHz R/W (operated using the basic clock with a frequency R/W 16 times the transfer clock frequency) 1011: Average transfer rate operation at 230.
ACS 4 ACS 2 ACS 1 ACS 0 Average Transfer Rate System Clock (φ) Operating Clock 1 0 1 1 230.392 kbps 20 MHz Transfer rate × 16 1 1 0 0 115.196 kbps 24 MHz Transfer rate × 16 1 1 0 1 230.392 kbps 24 MHz Transfer rate × 16 1 1 1 0 460.784 kbps 24 MHz Transfer rate × 16 1 1 1 1 720 kbps 24 MHz Transfer rate × 8 Rev. 3.
14.4 Operation in Asynchronous Mode Figure 14.3 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication.
14.4.1 Data Transfer Format Table 14.11 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, see section 14.5, Multiprocessor Communication Function. Table 14.
14.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Since receive data is latched internally at the rising edge of the 8th pulse of the basic clock, data is latched at the middle of each bit, as shown in figure 14.4.
14.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin.
Figure 14.6 Basic Clock Examples When Average Transfer Rate is Selected (1) Rev. 3.00, 03/04, page 384 of 830 1 1 2 2 4 5 1 1 2 2 8 7 3 3 9 10 11 12 13 14 4 5 7 8 15 16 7 Average error rate = –0.043% Average transfer rate = 3.6848 MHz/8= 460.606 kbps 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 1 1 bit = Basic clock × 8* 3.6848 MHz 4 5 6 5.333 MHz 6 Average error rate = –0.
Figure 14.7 Basic Clock Examples When Average Transfer Rate is Selected (2) Rev. 3.00, 03/04, page 385 of 830 1 1 2 2 3 3 4 5 1 1 2 2 3 3 1 1 2 2 4 5 13 14 15 16 7 8 9 10 11 12 4 5 7 5.76 MHz 4 5 6 6 8 13 14 15 16 7 Average error rate = –0% Average transfer rate = 5.76 MHz/8 = 720 kbps 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 Average error rate = –0.
14.4.5 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 14.8. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1.
14.4.6 Serial Data Transmission (Asynchronous Mode) Figure 14.9 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
[1] Initialization Start transmission [2] Read TDRE flag in SSR [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
14.4.7 Serial Data Reception (Asynchronous Mode) Figure 14.11 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2.
Table 14.12 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.12 shows a sample flowchart for serial data reception. Table 14.
Initialization [1] Start reception [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing and break detection: [2] If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After performing the Yes appropriate error processing, ensure PER ∨ FER ∨ ORER = 1 that the ORER, PER, and FER flags are [3] all cleared to 0. Reception cannot be No Error processing resumed if any of these flags are set to 1.
[3] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 No PER = 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 14.12 Sample Serial Reception Flowchart (2) Rev. 3.
14.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code.
Transmitting station Serial communication line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) (MPB = 0) ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID Legend MPB: Multiprocessor bit Figure 14.13 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Rev.
14.5.1 Multiprocessor Serial Data Transmission Figure 14.14 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode.
14.5.2 Multiprocessor Serial Data Reception Figure 14.16 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 14.15 shows an example of SCI operation for multiprocessor format reception.
Initialization [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [1] Start reception Set MPIE bit in SCR to 1 [2] ID reception cycle: Set the MPIE bit in SCR to 1. [2] [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station’s ID. If the data is not this station’s ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0.
[5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 14.16 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 3.
14.6 Operation in Clock Synchronous Mode Figure 14.17 shows the general format for clock synchronous communication. In clock synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next. In data reception, the SCI receives data in synchronization with the rising edge of the synchronization clock.
14.6.2 SCI Initialization (Clock Synchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 14.18. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1.
14.6.3 Serial Data Transmission (Clock Synchronous Mode) Figure 14.19 shows an example of SCI operation for transmission in clock synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
[1] Initialization Start transmission Read TDRE flag in SSR [2] No TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? [3] Yes [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
14.6.4 Serial Data Reception (Clock Synchronous Mode) Figure 14.21 shows an example of SCI operation for reception in clock synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR. 2.
[1] Initialization Start reception [2] Read ORER flag in SSR Yes ORER = 1 [3] No Error processing (Continued below) Read RDRF flag in SSR [4] No RDRF = 1 Yes Read receive data in RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [5] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
14.6.5 Simultaneous Serial Data Transmission and Reception (Clock Synchronous Mode) Figure 14.23 shows a sample flowchart for simultaneous serial transmit and receive operations. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations.
Initialization [1] [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt.
14.7 Smart Card Interface Description The SCI supports the IC card (smart card) interface based on the ISO/IEC 7816-3 (Identification Card) standard as an enhanced serial communication interface function. Smart card interface mode can be selected using the appropriate register. 14.7.1 Sample Connection Figure 14.24 shows a sample connection between the smart card and this LSI.
In normal transmission/reception Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp D7 Dp Output from the transmitting station When a parity error is generated Ds D0 D1 D2 D3 D4 D5 D6 DE Output from the transmitting station Output from the receiving station [Legend] Ds: D0 to D7: Dp: DE: Start bit Data bits Parity bit Error signal Figure 14.
which is prescribed by the smart card standard, and corresponds to state Z. Since the SINV bit of this LSI only inverts data bits D7 to D0, write 1 to the O/E bit in SMR to invert the parity bit in both transmission and reception. 14.7.3 Block Transfer Mode Block transfer mode is different from normal smart card interface mode in the following respects. • If a parity error is detected during reception, no error signal is output.
372 clock cycles 186 clock cycles 0 185 185 371 0 371 0 Internal basic clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 14.28 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock Frequency is 372 Times the Bit Rate) 14.7.5 Initialization Before starting transmitting and receiving data, initialize the SCI using the following procedure.
the end of initialization, TE and RE should be set to 0 and 1, respectively. Transmission completion can be verified by reading the TEND flag. 14.7.6 Serial Data Transmission (Except in Block Transfer Mode) Data transmission in smart card interface mode (except in block transfer mode) is different from that in normal serial communication interface mode in that an error signal is sampled and data is re-transmitted. Figure 14.29 shows the data re-transfer operation during transmission. 1.
(n + 1) th transfer frame Retransfer frame nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4 TDRE Transfer from TDR to TSR Transfer from TDR to TSR Transfer from TDR to TSR TEND [2] [3] FER/ERS [1] [3] Figure 14.29 Data Re-transfer Operation in SCI Transmission Mode Note that the TEND flag is set in different timings depending on the GM bit setting in SMR, which is shown in figure 14.30.
Start Initialization Start transmission ERS = 0? No Yes Error processing No TEND = 1? Yes Write data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit in SCR to 0 End Figure 14.31 Sample Transmission Flowchart Rev. 3.
14.7.7 Serial Data Reception (Except in Block Transfer Mode) Data reception in smart card interface mode is identical to that in normal serial communication interface mode. Figure 14.32 shows the data re-transfer operation during reception. 1. If a parity error is detected in receive data, the PER bit in SSR is set to 1. Here, an ERI interrupt request is generated if the RIE bit in SCR is set to 1. Clear the PER bit to 0 before the next parity bit is sampled. 2.
Start Initialization Start reception ORER = 0 and PER = 0? No Yes Error processing No RDRF = 1? Yes Read data from RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 Figure 14.33 Sample Reception Flowchart 14.7.8 Clock Output Control Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set to 1. Specifically, the minimum width of a clock pulse can be specified. Figure 14.
At power-on and transitions to/from software standby mode, use the following procedure to secure the appropriate clock duty ratio. At Power-On: To secure the appropriate clock duty ratio simultaneously with power-on, use the following procedure. 1. Initially, port input is enabled in the high-impedance state. To fix the potential level, use a pull-up or pull-down resistor. 2. Fix the SCK pin to the specified output using the CKE1 bit in SCR. 3. Set SMR and SCMR to enable smart card interface mode. 4.
14.8 IrDA Operation IrDA operation can be used with SCI_1. Figure 14.36 shows an IrDA block diagram. If the IrDA function is enabled using the IrE bit in SCICR, the TxD1 and RxD1 signals for SCI_1 are allowed to encode and decode the waveform based on the IrDA standard version 1.0 (function as the IrTxD and IrRxD pins). Connecting these pins to the infrared data transceiver achieves infrared data communication based on the system defined by the IrDA standard version 1.0.
UART frame Data Start bit 0 1 0 1 0 0 Stop bit 1 Transmission 1 0 1 Reception IR frame Data Start bit 0 1 Bit cycle 0 1 0 0 Stop bit 1 1 0 1 Pulse width is 1.6 µs to 3/16 bit cycle Figure 14.37 IrDA Transmission and Reception Reception: During reception, IR frames are converted to UART frames using the IrDA interface before inputting to SCI_1. Data of level 0 is output each time a high-level pulse is detected and data of level 1 is output when no pulse is detected in a bit cycle.
Table 14.13 IrCKS2 to IrCKS0 Bit Settings Bit Rate (bps) (Upper Row) / Bit Interval × 3/16 (µs) (Lower Row) Operating Frequency 2400 9600 19200 38400 57600 115200 φ (MHz) 78.13 19.53 9.77 4.88 3.26 1.63 5 011 011 011 011 011 011 6 100 100 100 100 100 100 6.144 100 100 100 100 100 100 7.3728 100 100 100 100 100 100 8 100 100 100 100 100 100 9.8304 100 100 100 100 100 100 10 100 100 100 100 100 100 12 101 101 101 101 101 101 12.
14.9 Interrupt Sources 14.9.1 Interrupts in Normal Serial Communication Interface Mode Table 14.13 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated.
14.9.2 Interrupts in Smart Card Interface Mode Table 14.15 shows the interrupt sources in smart card interface mode. A TEI interrupt request cannot be used in this mode. Table 14.
14.10 Usage Notes 14.10.1 Module Stop Mode Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, see section 23, Power-Down Modes. 14.10.2 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly.
14.10.6 Restrictions on Using DTC When the external clock source is used as a synchronization clock, update TDR by the DTC and wait for at least five φ clock cycles before allowing the transmit clock to be input. If the transmit clock is input within four clock cycles after TDR modification, the SCI may malfunction (figure 14.38). When using the DTC to read RDR, be sure to set the receive end interrupt source (RXI) as a DTC activation source.
Reception: Before making the transition to module stop, software standby, watch, sub-active, or sub-sleep mode, stop reception (RE = 0). RSR, RDR, and SSR are reset. If transition is made during data reception, the data being received will be invalid. To receive data in the same reception mode after mode cancellation, set RE to 1, and then start reception. To receive data in a different reception mode, initialize the SCI first. Figure 14.42 shows a sample flowchart for mode transition during reception.
Transmission start Transition to Software standby Transmission end software standby mode cancelled mode TE bit SCK output pin TxD output pin Port input/output Port input/output High output Start Stop Port input/output SCI TxD output Port Port High output SCI TxD output Figure 14.
Reception Read RDRF flag in SSR RDRF = 1 No [1] [1] Data being received will be invalid. Yes Read receive data in RDR [2] Module stop, watch, sub-active, and subsleep modes are included. RE = 0 [2] Make transition to software standby mode etc. Cancel software standby mode etc. Change operating mode? No Yes Initialization RE = 1 Start reception Figure 14.42 Sample Flowchart for Mode Transition during Reception Rev. 3.
14.10.8 Notes on Switching from SCK Pins to Port Pins When SCK pins are switched to port pins after transmission has completed, pins are enabled for port output after outputting a low pulse of half a cycle as shown in figure 14.43. Low pulse of half a cycle SCK/Port 4. Low pulse output 1. Transmission end Data Bit 6 Bit 7 2. TE = 0 TE 3. C/A = 0 C/A CKE1 CKE0 Figure 14.
14.11 CRC Operation Circuit The cyclic redundancy check (CRC) operation circuit detects errors in data blocks. 14.11.1 Features The features of the CRC operation circuit are listed below. • • • • CRC code generated for any desired data length in an 8-bit unit CRC operation executed on eight bits in parallel One of three generating polynomials selectable CRC code generation for LSB-first or MSB-first communication selectable Figure 14.45 shows a block diagram of the CRC operation circuit.
CRC Control Register (CRCCR): CRCCR initializes the CRC operation circuit, switches the operation mode, and selects the generating polynomial. Bit Bit Name Initial Value R/W Description 7 DORCLR 0 W CRCDOR Clear Setting this bit to 1 clears CRCDOR to H′0000. 6 to 3 All 0 R Reserved The initial value should not be changed. 2 LMS 0 R/W CRC Operation Switch Selects CRC code generation for LSB-first or MSBfirst communication. 0: Performs CRC operation for LSB-first communication.
14.11.3 CRC Operation Circuit Operation The CRC operation circuit generates a CRC code for LSB-first/MSB-first communications. An example in which a CRC code for hexadecimal data H'F0 is generated using the X16 + X12 + X5 + 1 polynomial with the G1 and G0 bits in CRCCR set to B'11 is shown below. 1. Write H'83 to CRCCR 2.
1. Serial reception (LSB first) Data CRC code 7 1 1 1 1 0 1 1 F 0 7 1 1 0 7 0 0 8 2. Write H'83 to CRCCR 1 1 1 7 1 1 F 1 1 0 0 F 0 0 0 0 0 0 0 0 1 1 CRCDIR 1 0 1 1 1 0 0 CRC code generation CRCDOR clearing 0 7 0 7 CRCDORH 0 0 0 0 0 0 0 0 CRCDORH 1 1 1 1 0 1 1 1 CRCDORL 0 0 0 0 0 0 0 0 CRCDORL 1 0 0 0 1 1 1 1 1 0 1 1 1 4. Write H'8F to CRCDIR 5. Write H'F7 to CRCDIR 7 CRCDIR 1 7 0 0 Input 0 7 0 0 0 1 3.
1. Serial reception (MSB first) Data CRC code 7 Input 1 1 1 1 0 0 0 F 0 7 0 1 0 2. Write H'87 to CRCCR 1 1 0 1 1 E 0 7 1 0 0 0 F 0 1 1 1 0 0 0 1 1 1 CRCDIR 1 0 1 1 1 0 0 0 0 CRC code generation CRCDOR clearing 0 7 0 7 CRCDORH 0 0 0 0 0 0 0 0 CRCDORH 1 1 1 0 1 1 1 1 CRCDORL 0 0 0 0 0 0 0 0 CRCDORL 0 0 0 1 1 1 1 1 1 1 1 1 1 4. Write H'EF to CRCDIR 5. Write H'1F to CRCDIR 7 CRCDIR 1 7 0 1 1 1 F 7 0 0 1 3.
14.11.4 Note on CRC Operation Circuit Note that the sequence to transmit the CRC code differs between LSB-first transmission and MSB-first transmission. 1. CRC code generation After specifying the operation method, write data to CRCDIR in the sequence of (1) → (2) → (3) → (4). 7 0 (1) → (2) → (3) → (4) CRCDIR CRC code generation 0 7 CRCDORH (5) CRCDORL (6) 2.
Rev. 3.
Section 15 I2C Bus Interface (IIC) This LSI has a six-channel I2C bus interface (IIC). The I2C bus interface conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. 15.
Figure 15.1 shows a block diagram of the I2C bus interface. Figure 15.2 shows an example of I/O pin connections to external circuits. Since I2C bus interface I/O pins are different in structure from normal port pins, they have different specifications for permissible applied voltages. For details, see section 25, Electrical Characteristics.
VCC VDD VCC SCL SCL SDA SDA SCL in SDA out (Master) SCL in This LSI SCL out SCL out SDA in SDA in SDA out SDA out (Slave 1) SCL SDA SDA in SCL SDA SCL out SCL in (Slave 2) Figure 15.2 I2C Bus Interface Connections (Example: This LSI as Master) Rev. 3.
15.2 Input/Output Pins Table 15.1 summarizes the input/output pins used by the I2C bus interface. Table 15.
15.3 Register Descriptions The I2C bus interface has the following registers. Registers ICDR and SARX and registers ICMR and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit is set to 1, ICMR and ICDR can be accessed. The IIC registers are allocated to the same address.
If IIC is in receive mode and no previous data remains in ICDRR (the ICDRF flag is 0), data is transferred automatically from ICDRS to ICDRR, following reception of one frame of data using ICDRS. If additional data is received while the ICDRF flag is 1, data is transferred automatically from ICDRS to ICDRR by reading from ICDR. In transmit mode, no data is transferred from ICDRS to ICDRR. Always set IIC to receive mode before reading from ICDR.
15.3.3 Second Slave Address Register (SARX) SARX sets the second slave address and selects the communication format. In slave mode, transmit/receive operations by the DTC are possible when the received address matches the second slave address. When the LSI is in slave mode with the I2C bus format selected, if the FSX bit is set to 0 and the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device.
• I2C bus format: addressing format with acknowledge bit • Clocked synchronous serial format: non-addressing format without acknowledge bit, for master mode only 15.3.4 I2C Bus Mode Register (ICMR) ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit in ICCR is set to 1. Bit Bit Name Initial Value R/W Description 7 MLS 0 R/W MSB-First/LSB-First Select 0: MSB-first 1: LSB-first 2 Set this bit to 0 when the I C bus format is used.
Bit Bit Name 2 1 0 BC2 BC1 BC0 Initial Value R/W All 0 R/W Description Bit Counter These bits specify the number of bits to be transferred next. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than B'000, the setting should be made while the SCL line is low. The bit counter is initialized to B'000 when a start condition is detected. The value returns to B'000 at the end of a data transfer.
Table 15.3 I2C bus Transfer Rate (1) • TCSS = 0 STCR/ ICMR Bit 5 IICXn CKS2 CKS1 CKS0 Clock 0 0 Bit 4 Transfer Rate (MHz) IICX3 0 1 1 0 1 1 0 0 1 1 0 1 Bit 3 φ=5 φ=8 φ = 10 φ = 16 φ = 20 φ = 25 MHz MHz MHz MHz MHz MHz 1 φ = 33 MHz 1 892.9* 1 625.0* 0 φ/28 178.6 285.7 357.1 571.4* 714.3* 1 φ/40 125.0 200.0 250.0 400.0 500.0* 1 1 1178.6* 1 1 825.0* 1 1 1 0 φ/48 104.2 166.7 208.3 333.3 416.7* 520.8* 687.5* 1 φ/64 78.1 125.0 156.3 250.
Table 15.3 I2C bus Transfer Rate (2) • TCSS = 1 STCR/ ICMR Transfer Rate (MHz) IICX3 Bit 5 Bit 4 Bit 3 φ=5 φ=8 φ = 10 φ = 16 φ = 20 φ = 25 φ = 33 IICXn CKS2 CKS1 CKS0 Clock MHz MHz MHz MHz MHz MHz MHz 0 0 0 0 φ/56 89.3 142.9 178.6 285.7 357.1 446.4* 589.3* 1 φ/80 62.5 100.0 125.0 200.0 250.0 312.5 412.5* 1 0 φ/96 52.1 83.3 104.2 166.7 208.3 260.4 343.8 1 φ/128 39.1 62.5 78.1 125.0 156.3 195.3 257.8 0 φ/160 31.3 50.0 62.5 100.0 125.0 156.
15.3.6 I2C Bus Control Register (ICCR) ICCR controls the I2C bus interface and performs interrupt flag confirmation. Bit Bit Name Initial Value R/W Description 7 ICE 0 R/W I2C Bus Interface Enable 2 2 0: I C bus interface modules are stopped and I C bus interface module internal state is initialized. SAR and SARX can be accessed. 2 1: I C bus interface modules can perform transfer and reception, they are connected to the SCL and SDA pins, 2 and the I C bus can be driven.
Bit Bit Name Initial Value R/W Description 5 4 MST TRS 0 0 R/W R/W [MST clearing conditions] (1) When 0 is written by software (2) When lost in bus contention in I2C bus format master mode [MST setting conditions] (1) When 1 is written by software (for MST clearing condition 1) (2) When 1 is written in MST after reading MST = 0 (for MST clearing condition 2) [TRS clearing conditions] (1) When 0 is written by software (except for TRS setting condition 3) (2) When 0 is written in TRS after reading TR
Bit 2 0 Bit Name BBSY SCP Initial Value 0 1 R/W Description 3 R/W* Bus Busy W Start Condition/Stop Condition Prohibit In master mode • Writing 0 in BBSY and 0 in SCP: A stop condition is issued • Writing 1 in BBSY and 0 in SCP: A start condition and a restart condition are issued In slave mode • Writing to the BBSY flag is disabled. [BBSY setting condition] • When the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued.
Bit 1 Bit Name IRIC Initial Value 0 R/W Description 1 R/(W)* I2C Bus Interface Interrupt Request Flag 2 Indicates that the I C bus interface has issued an interrupt request to the CPU. IRIC is set at different times depending on the FS bit in SAR and the WAIT bit in ICMR. See section 15.4.7, IRIC Setting Timing and SCL Control. The conditions under which IRIC is set also differ depending on the setting of the ACKE bit in ICCR.
Bit Bit Name 1 IRIC Initial Value 0 R/W Description 1 R/(W)* At the end of data transfer in clock synchronous serial format (rise of the 8th transmit/receive clock) When a start condition is detected with serial format selected When a condition occurs in which the ICDRE or ICDRF flag is set to 1.
When the DTC is used, IRIC is cleared automatically and transfer can be performed continuously without CPU intervention. The DTC does not support IIC_4 and IIC_5. When, with the I2C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags must be checked in order to identify the source that set IRIC to 1. Although each source has a corresponding flag, caution is needed at the end of a transfer. When the ICDRE or ICDRF flag is set, the IRTR flag may or may not be set.
Table 15.
Table 15.
MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDRF ICDRE State 0 0 1 0 0 1 Reception end with ICDRF=1 0 0 1 0 0 0↓ 0↓ 0↓ 0↓ ICDR read with the above state 0 0 1 0 0 1↑/0 *2 0 0 0 1↑ Automatic data transfer from ICDRS to ICDRR with the above state 0 0↓ 1↑/0 *3 0/1↑ *3 0↓ Stop condition detected [Legend] 0: 0-state retained 1: 1-state retained : Previous state retained 1↑: Set to 1 0↓: Cleare
15.3.7 I2C Bus Status Register (ICSR) ICSR consists of status flags. Also see tables 15.4 and 15.5. Bit Bit Name Initial Value R/W 7 ESTP 0 R/(W)* Error Stop Condition Detection Flag Description 2 This bit is valid in I C bus format slave mode. [Setting condition] When a stop condition is detected during frame transfer.
Bit Bit Name Initial Value R/W 4 AASX 0 R/(W)* Second Slave Address Recognition Flag Description 2 In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX.
Bit Bit Name Initial Value R/W 2 AAS 0 R/(W)* Slave Address Recognition Flag Description 2 In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected.
Bit Bit Name Initial Value R/W Description 0 ACKB 0 R/W Acknowledge Bit Stores acknowledge data.
15.3.8 I2C Bus Extended Control Register (ICXR) ICXR enables or disables the I2C bus interface interrupt generation and continuous receive operation, and indicates the status of receive/transmit operations. Bit Bit Name Initial Value R/W Description 7 STOPIM 0 R/W Stop Condition Interrupt Source Mask Enables or disables the interrupt generation when the stop condition is detected in slave mode.
Bit Bit Name Initial Value R/W Description 5 ICDRF 0 R Receive Data Read Request Flag Indicates the ICDR (ICDRR) status in receive mode. 0: Indicates that the data has been already read from ICDR (ICDRR) or ICDR is initialized. 1: Indicates that data has been received successfully and transferred from ICDRS to ICDRR, and the data is ready to be read out. [Setting conditions] • When data is received successfully and transferred from ICDRS to ICDRR.
Bit Bit Name Initial Value R/W 4 ICDRE 0 R Description Transmit Data Write Request Flag Indicates the ICDR (ICDRT) status in transmit mode. 0: Indicates that the data has been already written to ICDR (ICDRT) or ICDR is initialized. 1: Indicates that data has been transferred from ICDRT to ICDRS and is being transmitted, or the start condition has been detected or transmission has been complete, thus allowing the next data to be written to.
Bit Bit Name Initial Value R/W Description 3 ALIE 0 R/W Arbitration Lost Interrupt Enable Enables or disables IRIC flag setting and interrupt request when arbitration is lost. 0: Disables interrupt request when arbitration is lost. 1: Enables interrupt request when arbitration is lost. 2 ALSL 0 R/W Arbitration Lost Condition Select Selects the condition under which arbitration is lost.
15.3.9 I2C SMBus Control Register (ICSMBCR) ICSMBCR is used to support the System Management Bus (SMBus) specifications. To support the SMBus specification, SDA output data hold time should be specified in the range of 300 ns to 1000 ns. Table 15.6 shows the relationship between the ICSMBCR setting and output data hold time. When the SMBus is not supported, the initial value should not be changed. ICSMBCR is enabled to access when bit MSTP4 is cleared to 0.
Table 15.6 Output Data Hold Time Output Data Hold Time (ns) φ=5 MHz φ = 6.6 φ = 8 MHz MHz φ = 10 MHz φ = 13.3 φ = 16 φ = 20 φ = 25 MHz MHz MHz MHz φ = 33 MHz Min. 400 303 250* 200* 150* 125* 100* 80* 61* Max. 600 455 375 300 226* 188* 150* 120* 91* Min. 600 455 375 300 226* 188* 150* 120* 91* Min./ SMBnE FSEL1 FSEL0 Max. 0 1 0 0 1 1 0 1 Notes: * Max. 1000* 758 625 500 376 313 250* 200* 152* Min.
15.4 Operation 15.4.1 I2C Bus Data Format The I2C bus interface has an I2C bus format and a serial format. The I2C bus formats are addressing formats with an acknowledge bit. These are shown in figures 15.3 (a) and (b). The first frame following a start condition always consists of 9 bits. The serial format is a non-addressing format with no acknowledge bit. This is shown in figure 15.4. Figure 15.5 shows the I2C bus timing. The symbols used in figures 15.3 to 15.5 are explained in table 15.8.
SDA SCL S 1–7 8 9 SLA R/W A 1–7 DATA 8 9 A 1–7 DATA 8 9 A/A P Figure 15.5 I2C Bus Timing Table 15.8 I2C Bus Data Format Symbols Symbol Description S Start condition. The master device drives SDA from high to low while SCL is high SLA Slave address. The master device selects the slave device. R/W Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0 A Acknowledge.
15.4.2 Initialization Initialize the IIC by the procedure shown in figure 15.6 before starting transmission/reception of data.
Figure 15.7 shows the sample flowchart for the operations in master transmit mode. Start Initialize IIC [1] Initialization Read BBSY in ICCR [2] Test the status of the SCL and SDA lines. No BBSY = 0? Yes Set MST = 1 and TRS = 1 in ICCR [3] Select master transmit mode. Set BBSY =1 and SCP = 0 in ICCR [4] Start condition issuance Read IRIC in ICCR [5] Wait for a start condition generation No IRIC = 1? Yes Write transmit data in ICDR [6] Set transmit data for the first byte (slave address + R/W).
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Initialize the IIC as described in section 15.4.2, Initialization. Read the BBSY flag in ICCR to confirm that the bus is free. Set bits MST and TRS to 1 in ICCR to select master transmit mode. Write 1 to BBSY and 0 to SCP in ICCR. This changes SDA from high to low when SCL is high, and generates the start condition. Then the IRIC and IRTR flags are set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt request is sent to the CPU.
Start condition generation SCL (master output) 1 2 3 4 5 6 7 SDA (master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 9 Bit 0 R/W Slave address SDA (slave output) 8 1 2 Bit 7 Bit 6 Data 1 [7] A [5] ICDRE IRIC Interrupt request Interrupt request IRTR ICDRT Data 1 Address + R/W ICDRS Address + R/W Data 1 Note: Do not set ICDR during this period.
15.4.4 Master Receive Operation In I2C bus format master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. The slave device transmits data. The master device transmits data containing the slave address and R/W (1: read) in the first frame following the start condition issuance in master transmit mode, selects the slave device, and then switches the mode for receive operation. Receive Operation Using the HNDS Function (HNDS = 1): Figure 15.
The reception procedure and operations by which the data reception process is provided in 1-byte units with SCL fixed low at each data reception are described below. [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 (acknowledge data setting). Set the HNDS bit in ICXR to 1. Clear the IRIC flag to 0 to determine the end of reception.
Master receive mode Master transmit mode SCL is fixed low until ICDR is read SCL (master output) SDA (slave output) 9 1 2 Bit 6 Bit 7 A 3 Bit 5 SCL is fixed low until ICDR is read 4 Bit 4 5 6 Bit 3 Bit 2 7 8 Bit 1 Bit 0 1 2 Bit 7 Bit 6 9 [3] Data 1 SDA (master output) Data 2 A IRIC IRTR ICDRF ICDRR Data 1 Undefined value User processing [1] TRS cleared to 0 [6] ICDR read (Data 1) [4] IRIC clear [2] ICDR read (Dummy read) [1] IRIC clear Figure 15.
Receive Operation Using the Wait Function: Figures 15.13 and 15.14 show the sample flowcharts for the operations in master receive mode (WAIT = 1). Master receive mode Set TRS = 0 in ICCR [1] Select receive mode. Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC in ICCR Set WAIT = 1 in ICMR [2] Start receiving. The first read is a dummy read.
Master receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR [1] Select receive mode. Clear IRIC in ICCR Set WAIT = 0 in ICMR Read ICDR [2] Start receiving. The first read is a dummy read. Read IRIC in ICCR No IRIC = 1? [3] Wait for a receive wait (Set IRIC at the fall of the 8 th clock) Yes No Set ACKB = 1 in ICSR [7] Set acknowledge data for the last reception. Set TRS = 1 in ICCR [9] Set TRS for stop condition issuance Clear IRIC in ICCR [14] Clear IRIC.
[1] [2] [3] [4] [5] [6] Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 to set the acknowledge data. Clear the HNDS bit in ICXR to 0 to cancel the handshake function. Clear the IRIC flag to 0, and then set the WAIT bit in ICMR to 1. When ICDR is read (dummy data is read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock.
[13] [14] [15] [16] [17] Read the IRTR flag in ICSR. If the IRTR flag is 0, execute step [14] to clear the IRIC flag to 0 to release the wait state. If the IRTR flag is 1 and data reception is complete, execute step [15] to issue the stop condition. If IRTR flag is 0, clear the IRIC flag to 0 to release the wait state. Execute step [12] to read the IRIC flag to detect the end of reception. Clear the WAIT bit in ICMR to cancel the wait mode. Clearing of the IRIC flag should be done while WAIT = 0.
[8] Wait for one clock pulse Stop condition generation SCL (master output) 8 9 SDA Bit 0 (slave output) Data 2 [3] SDA (master output) 1 2 3 4 5 6 7 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data 3 [3] A 9 [12] [12] A IRIC IRTR [4] IRTR=0 ICDR Data 1 User processing [13] IRTR=0 [4] IRTR=1 [13] IRTR=1 Data 2 [6] IRIC clear (to end wait insertion) [11] IRIC clear [10] ICDR read (Data 2) [9] Set TRS=1 [7] Set ACKB=1 Data 3 [15] WAIT cleared to 0, IRIC clear [14] IR
Receive Operation Using the HNDS Function (HNDS = 1): Figure 15.17 shows the sample flowchart for the operations in slave receive mode (HNDS = 1). Slave receive mode Initialize IIC Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR and HNDS = 1 in ICXR Clear IRIC in ICCR ICDRF = 1? No [1] Initialization. Select slave receive mode. [2] Read the receive data remaining unread.
The reception procedure and operations using the HNDS bit function by which data reception process is provided in 1-byte unit with SCL being fixed low at every data reception, are described below. [1] Initialize the IIC as described in section 15.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS bit to 1 and the ACKB bit to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception. [2] Confirm that the ICDRF flag is 0.
Start condition generation SCL (Pin waveform) SCL (master output) SCL (slave output) SDA (master output) SDA (slave output) [7] SCL is fixed low until ICDR is read 1 2 3 4 5 6 7 8 9 1 2 1 2 3 4 5 6 7 8 9 1 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Slave address Bit 7 R/W Bit 6 Data 1 [6] A Interrupt request occurrence IRIC ICDRF Address+R/W ICDRS ICDRR Address+R/W Undefined value User processing [2] ICDR read [8] IRIC clear [10] ICDR read (dummy read)
Continuous Receive Operation: Figure 15.20 shows the sample flowchart for the operations in slave receive mode (HNDS = 0). Slave receive mode Set MST = 0 and TRS = 0 in ICCR [1] Select slave receive mode. Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC in ICCR ICDRF = 1? No [2] Read the receive data remaining unread.
The reception procedure and operations in slave receive are described below. [1] Initialize the IIC as described in section 15.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS and ACKB bits to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception. [2] Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read the ICDR and then clear the IRIC flag to 0.
Start condition issuance SCL (master output) SDA (master output) 1 2 3 4 5 6 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Slave address 8 9 1 Bit 7 Bit 0 R/W SDA (slave output) [6] 2 3 4 Bit 6 Bit 5 Bit 4 Data 1 A IRIC ICDRF ICDRS Address+R/W Data 1 [7] ICDRR Address+R/W User processing [8] IRIC clear [10] ICDR read Figure 15.
15.4.6 Slave Transmit Operation If the slave address matches to the address in the first frame (address reception frame) following the start condition detection when the 8th bit data (R/W) is 1 (read), the TRS bit in ICCR is automatically set to 1 and the mode changes to slave transmit mode. Figure 15.23 shows the sample flowchart for the operations in slave transmit mode.
[1] Initialize slave receive mode and wait for slave address reception. [2] When the slave address matches in the first frame following detection of the start condition, the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. If the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to 1, and the mode changes to slave transmit mode automatically. The IRIC flag is set to 1 at the rise of the 9th clock.
Slave transmit mode Slave receive mode SCL (master output) 8 SDA (slave output) 9 1 2 A Bit 7 Bit 6 3 4 5 6 7 8 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data 1 [2] SDA (master output) R/W 9 1 2 Bit 7 Bit 6 [4] Data 2 A IRIC ICDRE ICDR User processing Data 2 Data 1 [3] IRIC clear [3] ICDR write [3] IRIC clear [5] IRIC clear [5] ICDR write Figure 15.24 Slave Transmit Mode Operation Timing Example (MLS = 0) Rev. 3.
15.4.7 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is automatically held low after one frame has been transferred; this timing is synchronized with the internal clock. Figures 15.25 to 15.27 show the IRIC set timing and SCL control.
When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted) SCL SDA 8 9 1 2 3 8 A 1 2 3 IRIC User processing Clear IRIC Clear IRIC (a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception. SCL SDA 8 9 1 8 A 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read from ICDR (receive) Clear IRIC (b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception. Figure 15.26 IRIC Setting Timing and SCL Control (2) Rev. 3.
When FS = 1 and FSX = 1 (clocked synchronous serial format) SCL SDA 7 8 7 8 1 1 2 2 3 3 4 4 IRIC User processing Clear IRIC (a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception. SCL SDA 7 8 1 7 8 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read from ICDR (receive) Clear IRIC (b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception. Figure 15.27 IRIC Setting Timing and SCL Control (3) 15.4.
The acknowledge bit may indicate specific events such as completion of receive data processing for some receiving devices, and for other receiving devices, the acknowledge bit may be held to 1, indicating no specific events. The I2C bus format provides for selection of the slave device and transfer direction by means of the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication of the last frame, and so on.
15.4.9 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 15.28 shows a block diagram of the noise canceler. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) pin input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held.
• The value of the ICMR register bit counter (BC2 to BC0) • Generated interrupt sources (interrupt sources transferred to the interrupt controller) Notes on Initialization: • Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be taken as necessary. • Basically, other register flags are not cleared either, and so flag clearing measures must be taken as necessary.
15.5 Interrupt Source The IIC interrupt source is IICI. The IIC interrupt sources and their priority order are shown in table 15.10. Each interrupt source is enabled or disabled by the ICCR interrupt enable bit and transferred to the interrupt controller independently. The IICI0 to IICI3 interrupts can be used as sources of activating the on-chip DTC. Table 15.
15.6 Usage Notes 1. In master mode, if an instruction to generate a start condition is immediately followed by an instruction to generate a stop condition, neither condition will be output correctly. To output consecutive start and stop conditions*, after issuing the instruction that generates the start condition, read the relevant DR registers of I2C bus output pins, check that SCL and SDA are both low. If the ICE bit is set to 1, pin state can be monitored by reading DR register.
4. SCL and SDA input is sampled in synchronization with the internal clock. The AC timing therefore depends on the system clock cycle tcyc, as shown in section 25, Electrical Characteristics. Note that the I2C bus interface AC timing specification will not be met with a system clock frequency of less than 5 MHz. 5. The I2C bus interface specification for the SCL rise time tsr is 1000 ns or less (300 ns for highspeed mode).
tBUFO fails to meet the I2C bus interface specifications at any frequency. The solution is either (a) to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a stop condition and issuance of a start condition, or (b) to select devices whose input timing permits this output timing for use as slave devices connected to the I2C bus.
Table 15.13 I2C Bus Timing (with Maximum Influence of tSr/tSf) Time Indication (at Maximum Transfer Rate) [ns] I2C Bus tcyc tSr/tSf Specifi- φ= φ= φ= φ= φ= φ= φ= Indi- Influence cation 5 MHz 8 MHz 10 16 20 25 33 Item cation (Max.) (Min.) MHz MHz MHz MHz MHz tSCLHO 0.
Time Indication (at Maximum Transfer Rate) [ns] I2C Bus tcyc tSr/tSf Specifi- φ= φ= φ= φ= φ= Indi- Influence cation φ= φ= 10 16 20 25 33 Item cation (Max.) (Min.) 5 MHz 8 MHz MHz MHz MHz MHz MHz tSDAHO 3 tcyc 0 0 600 375 300 188 150 120 91 0 0 600 375 300 188 150 120 91 Standard mode High-speed mode Notes: 1. Does not meet the I2C bus interface specification.
Stop condition Start condition (a) SDA Bit 0 A SCL 8 9 Internal clock BBSY bit Master receive mode ICDR read disabled period Execution of instruction for issuing stop condition (write 0 to BBSY and SCP) Confirmation of stop condition issuance (read BBSY = 0) Start condition issuance Figure 15.29 Notes on Reading Master Receive Data Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B′11 in ICXR. 8. Notes on start condition issuance for retransmission Figure 15.
No IRIC = 1? [1] Wait for end of 1-byte transfer [1] Yes [2] Determine whether SCL is low Clear IRIC in ICCR [3] Issue start condition instruction for retransmission Read SCL pin No SCL = Low? [4] Determine whether start condition is generated or not [2] Yes [5] Set transmit data (slave address + R/W) Set BBSY = 1, SCP = 0 (ICCR) [3] No IRIC = 1? [4] Note: Program so that processing from [3] to [5] is executed continuously.
9. Note on when I2C bus interface stop condition instruction is issued In a situation where the rise time of the 9th clock of SCL exceeds the stipulated value because of a large bus load capacity or where a slave device in which a wait can be inserted by driving the SCL pin low is used, the stop condition instruction should be issued after reading SCL after the rise of the 9th clock pulse and determining that it is low.
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in ICXR. 11. Note on ICDR register read and ICCR register access in slave transmit mode In I2C bus interface slave transmit mode, do not read ICDR or do not read/write from/to ICCR during the time shaded in figure 15.33.
12. Note on TRS bit setting in slave mode In I2C bus interface slave mode, if the TRS bit value in ICCR is set after detecting the rising edge of the 9th clock pulse or the stop condition before detecting the next rising edge on the SCL pin (the time indicated as (a) in figure 15.34), the bit value becomes valid immediately when it is set. However, if the TRS bit is set during the other time (the time indicated as (b) in figure 15.
14. Note on ACKE and TRS bits in slave mode In the I2C bus interface, if 1 is received as the acknowledge bit value (ACKB = 1) in transmit mode (TRS = 1) and then the address is received in slave mode without performing appropriate processing, interrupt handling may start at the rising edge of the 9th clock pulse even when the address does not match.
• Arbitration is lost • The AL flag in ICSR is set to 1 I2C bus interface (Master transmit mode) S SLA R/W A DATA1 Transmit data match Transmit timing match Other device (Master transmit mode) S SLA R/W A Transmit data does not match DATA2 A DATA3 A Data contention I2C bus interface (Slave receive mode) S SLA R/W A • Receive address is ignored SLA R/W A DATA4 A • Automatically transferred to slave receive mode • Receive data is recognized as an address • When the receive data ma
Section 16 LPC Interface (LPC) This LSI has an on-chip LPC interface. The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz PCI clock. It uses four signal lines for address/data, and one for host interrupt requests. The LPC interface operates as a slave and supports only I/O read cycle and I/O write cycle transfer. It is also provided with power-down functions that can control the PCI clock and shut down the LPC interface. 16.
Figure 16.1 shows a block diagram of the LPC.
16.2 Input/Output Pins Table 16.1 lists the input and output pins of the LPC. Table 16.
16.3 Register Descriptions The LPC registers are listed in the following. Though this LSI accesses these registers as a slave, some of them can be accessed from the host. For details, see each register description.
BT mode: The following registers are required when BT mode is used. • BT status register 0 (BTSR0) • BT status register 1 (BTSR1) • BT control status register 0 (BTCSR0) • BT control status register 1 (BTCSR1) • BT control register (BTCR) • BT data buffer (BTDTR) • BT interrupt mask register (BTIMSR) • BT FIFO valid size register 0 (BTFVSR0) • BT FIFO valid size register 1 (BTFVSR1) Rev. 3.
16.3.1 Host Interface Control Registers 0 and 1 (HICR0, HICR1) HICR0 and HICR1 contain control bits that enable or disable LPC interface functions, control bits that determine pin output and the internal state of the LPC interface, and status flags that monitor the internal state of the LPC interface. HICR0 and HICR1 are initialized to H'00 by a reset or in hardware standby mode.
R/W Bit Bit Name Initial Value Slave Host Description 4 FGA20E 0 R/W Fast A20 Gate Function Enable Enables or disables the fast A20 gate function. When the fast A20 gate is disabled, the normal A20 gate can be implemented by firmware operation of the PD3 output. When the fast A20 gate function is enabled, the DDR bit for PD3 must not be set to 1.
R/W Initial Bit Bit Name Value Slave Host Description 2 PMEE 0 R/W PME Output Enable Controls PME output in combination with the PMEB bit in HICR1. PME pin output is open-drain, and an external pull-up resistor is needed to pull the output up to VCC When the PME output function is used, the DDR bit for PD2 must not be set to 1.
• HICR1 R/W Bit Bit Name Initial Value Slave Host Description 7 LPCBSY 0 R LPC Busy Indicates that the LPC interface is processing a transfer cycle.
R/W Bit Bit Name Initial Value Slave Host Description 5 IRQBSY 0 R SERIRQ Busy Indicates that the LPC interface's SERIRQ signal is engaged in transfer processing.
R/W Bit Bit Name Initial Value Slave Host Description 3 SDWNB 0 R/W LPC Software Shutdown Bit Controls LPC interface shutdown. For details of the LPC shutdown function, and the scope of initialization by an LPC reset and an LPC shutdown, see section 16.4.6, LPC Interface Shutdown Function (LPCPD).
16.3.2 Host Interface Control Registers 2 and 3 (HICR2, HICR3) The bits 6 to 0 in HICR2 control interrupts from the LPC interface module to the slave processor (this LSI). HICR3 and the bit 7 of HICR2 monitor the LPC interface pin states. Bits 6 to 0 in HICR2 are initialized to H'00 by a reset or in hardware standby mode. The states of the other bits are determined by the pin states.
R/W Bit Bit Name Initial Value Slave Host Description 4 ABRT 0 R/(W)* LPC Abort Interrupt Flag Interrupt flag that generates an ERRI interrupt when a forced termination (abort) of an LPC transfer cycle occurs.
R/W Bit Bit Name Initial Value Slave Host Description 1 IBFIE1 0 R/W IDR1 Receive Completion Interrupt Enable Enables or disables IBFI1 interrupt to the slave processor (this LSI). 0: Input data register IDR1 receive completed interrupt requests disabled 1: Input data register IDR1 receive completed interrupt requests enabled 0 ERRIE 0 R/W Error Interrupt Enable Enables or disables ERRI interrupt to the slave processor (this LSI).
16.3.3 Host Interface Control Register 4 (HICR4) HICR4 controls the selection of access channel when setting addresses for LPC channels 1 and 2, and the operation of KCS, SMIC, and BT interfaces included in channel 3. R/W Bit Bit Name Initial Value Slave Host Description 7 LADR12SEL 0 R/W Switches the access channel of LADR12H, LAD12L.
16.3.4 LPC Channel 3 Address Register H, L (LADR3H, LADR3L) LADR3 comprises two 8-bit readable/writable registers that perform LPC channel 3 host address setting and control the operation of the bidirectional data registers. The contents of the address field in LADR3 must not be changed while channel 3 is operating (while LPC3E is set to 1).
When LPC3E = 1, an I/O address received in an LPC I/O cycle is compared with the contents of LADR3. When determining an IDR3, ODR3, or STR3 address match, bit 0 in LADR3 is regarded as 0, and the value of bit 2 is ignored. When determining a TWR0 to TWR15 address match, bit 4 of LADR3 is inverted, and the values of bits 3 to 0 are ignored.
• KCS mode I/O Address Bits 15 to5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Transfer Cycle Host Register Selection Bits 15 to5 Bit 4 0 0 1 0 I/O write IDR3 write, C/D3 ← 0 Bits 15 to5 Bit 4 0 0 1 1 I/O write IDR3 write, C/D3 ← 1 Bits 15 to5 Bit 4 0 0 1 0 I/O read ODR3 read Bits 15 to5 Bit 4 0 0 1 1 I/O read STR3 read • BT mode I/O Address Bits 15 to5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Transfer Cycle Host Register Selection Bits 15 to5 Bit 4 0 1 0 0 I/O write BTCR write
• Notes on determining address match The IDR3/ODR3/STR3 addresses depend on mode.
16.3.5 LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L) LADR12H and LADR12L are temporary registers for accessing internal registers LADR1H, LADR1L, LADR2H, and LADR2L. When the LADR12SEL bit in HICR4 is 0, LPC channel 1 host addresses (LADR1H, LADR1L) are set through LADR12. The contents of the address field in LADR1 must not be changed while channel 1 is operating (while LPC1E is set to 1). When the LADR12SEL bit is 1, LPC channel 2 host addresses (LADR2H, LADR2L) are set through LADR12.
Table 16.4 Slave Selection Internal Registers Slave (R/W) Bus Width (B/W) LADR12SEL LADR12 Internal Register R/W B 0 LADR12H LADR1H R/W B 1 LADR12H LADR2H R/W B 0 LADR12L LADR1L R/W B 1 LADR12L LADR2L R/W W 0 LADR12H LADR12L LADR1H LADR1L R/W W 1 LADR12H LADR12L LADR2H LADR2L 16.3.6 Input Data Registers 1 to 3 (IDR1 to IDR3) The IDR registers are 8-bit read-only registers to the slave processor (this LSI), and 8-bit writeonly registers to the host processor.
16.3.8 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15) TWR0 to TWR15 are sixteen 8-bit readable/writable registers to both the slave processor (this LSI) and the host processor. In TWR0, however, two registers (TWR0MW and TWR0SW) are allocated to the same address for both the host address and the slave address.
16.3.9 Status Registers 1 to 3 (STR1 to STR3) The STR registers are 8-bit registers that indicate status information during LPC interface processing. Bits 3, 1, and 0 in STR1 to STR3 are read-only bits to both the host processor and the slave processor (this LSI). However, 0 only can be written from the slave processor (this LSI) to bit 0 in STR1 to STR3, and bits 6 and 4 in STR3, in order to clear the flags to 0.
R/W Bit Bit Name Initial Value Slave Host Description 1 IBF1 0 R R Input Data Register Full Indicates whether or not there is receive data in IDR1. This bit is an internal interrupt source to the slave processor (this LSI). The IBF1 flag setting and clearing conditions are different when the fast A20 gate is used. For details see table 16.7.
• STR2 R/W Bit Bit Name Initial Value Slave Host Description 7 6 5 4 DBU27 DBU26 DBU25 DBU24 All 0 3 C/D2 0 R/W R Defined by User The user can use these bits as necessary. R R Command/Data When the host processor writes to an IDR2 register, bit 2 of the I/O address is written into this bit to indicate whether IDR2 contains data or a command.
• STR3 (When TWRE = 1 or SELSTR3 = 0) R/W Bit Bit Name Initial Value Slave Host Description 7 IBF3B 0 R R Bidirectional Data Register Input Data Full Indicates whether or not there is receive data in TWR0 to TWR15. This is an internal interrupt source to the slave processor (this LSI).
R/W Bit Bit Name Initial Value Slave Host Description 4 SWMF 0 R/(W)* R Slave Write Mode Flag Indicates that slave write mode is entered by writing to TWR0 from the slave processor (this LSI). In the event of simultaneous writes by the master and the slave, the master write has priority.
R/W Bit Bit Name Initial Value Slave Host Description 0 OBF3A 0 R/(W)* R Output Data Register Full Indicates whether or not there is transmit data in ODR3. 0: There is not transmit data in ODR3 [Clearing condition] When the host processor reads ODR3 using I/O read cycle, or the slave processor writes 0 to the OBF3A bit 1: There is transmit data in ODR3 [Setting condition] When the slave processor writes to ODR3 Note: * Only 0 can be written to clear the flag.
R/W Bit Bit Name Initial Value Slave Host Description 1 IBF3A 0 R R Input Data Register Full Indicates whether or not there is receive data in IDR3. This bit is an internal interrupt source to the slave processor (this LSI).
16.3.10 SERIRQ Control Register 0 (SIRQCR0) The SIRQCR0 register contains status bits that indicate the SERIRQ operating mode and status bits that specify SERIRQ0 interrupt sources. The SIRQCR0 register is initialized to H'00 by a reset or in hardware standby mode. R/W Bit Bit Name Initial Value Slave Host Description 7 Q/C 0 R Quiet/Continuous Mode Flag Indicates the mode specified by the host at the end of an SERIRQ transfer cycle (stop frame).
R/W Bit Bit Name Initial Value Slave Host Description 4 SMIE3B 0 R/W Host SMI Interrupt Enable 3B Enables or disables a host SMI interrupt request when OBF3B is set by a TWR15 write.
R/W Bit Bit Name Initial Value Slave Host Description 2 SMIE2 0 R/W Host SMI Interrupt Enable 2 Enables or disables a host SMI interrupt request when OBF2 is set by an ODR2 write.
R/W Bit Bit Name Initial Value Slave Host Description 0 IRQ1E1 0 R/W Host IRQ1 Interrupt Enable 1 Enables or disables a HIRQ1 interrupt request when OBF1 is set by an ODR1 write. 0: HIRQ1 interrupt request by OBF1 and IRQ1E1 is disabled [Clearing conditions] • Writing 0 to IRQ1E1 • LPC hardware reset, LPC software reset • Clearing OBF1 to 0 1: HIRQ1 interrupt request by setting OBF1 to 1 is enabled [Setting condition] • Writing 1 after reading IRQ1E1 = 0 16.3.
R/W Bit Bit Name Initial Value Slave Host Description 7 IRQ11E3 0 R/W Host IRQ11 Interrupt Enable 3 Enables or disables a HIRQ11 interrupt request when OBF3A is set by an ODR3 write. 0: HIRQ11 interrupt request by OBF3A and IRQ11E3 is disabled [Clearing conditions] • Writing 0 to IRQ11E3 • LPC hardware reset, LPC software reset • Clearing OBF3A to 0 (when IEDIR3 = 0) 1: [When IEDIR3 = 0] HIRQ11 interrupt request by setting OBF3A to 1 is enabled [When IEDIR3 = 1] HIRQ11 interrupt is requested.
R/W Bit Bit Name Initial Value Slave Host Description 5 IRQ9E3 0 R/W Host IRQ9 Interrupt Enable 3 Enables or disables a HIRQ9 interrupt request when OBF3A is set by an ODR3 write. 0: HIRQ9 interrupt request by OBF3A and IRQ9E3 is disabled [Clearing conditions] • Writing 0 to IRQ9E3 • LPC hardware reset, LPC software reset • Clearing OBF3A to 0 (when IEDIR3 = 0) 1: [When IEDIR3 = 0] HIRQ9 interrupt request by setting OBF3A to 1 is enabled [When IEDIR3 = 1] HIRQ9 interrupt is requested.
R/W Bit Bit Name Initial Value Slave Host Description 3 IRQ11E2 0 R/W Host IRQ11 Interrupt Enable 2 Enables or disables a HIRQ11 interrupt request when OBF2 is set by an ODR2 write. 0: HIRQ11 interrupt request by OBF2 and IRQ11E2 is disabled [Clearing conditions] • Writing 0 to IRQ11E2 • LPC hardware reset, LPC software reset • Clearing OBF2 to 0 (when IEDIR = 0) 1: [When IEDIR = 0] HIRQ11 interrupt request by setting OBF2 to 1 is enabled [When IEDIR = 1] HIRQ11 interrupt is requested.
R/W Bit Bit Name Initial Value Slave Host Description 1 IRQ9E2 0 R/W Host IRQ9 Interrupt Enable 2 Enables or disables a HIRQ9 interrupt request when OBF2 is set by an ODR2 write. 0: HIRQ9 interrupt request by OBF2 and IRQ9E2 is disabled [Clearing conditions] • Writing 0 to IRQ9E2 • LPC hardware reset, LPC software reset • Clearing OBF2 to 0 (when IEDIR = 0) 1: [When IEDIR = 0] HIRQ9 interrupt request by setting OBF2 to 1 is enabled [When IEDIR = 1] HIRQ9 interrupt is requested.
16.3.12 SERIRQ Control Register 2 (SIRQCR2) The SIRQCR2 register contains status bits that specify an SERIRQ interrupt source. The SIRQCR2 register is initialized to H'00 by a reset or in hardware standby mode. R/W Bit Bit Name Initial Value Slave Host Description 7 IEDIR3 0 R/W Interrupt Enable Direct Mode 3 Specifies whether SERIRQ interrupt sources (SMI, HIRQ6, and HIRQ9 to HIRQ11) of LPC channel 3 are generated in relation to OBF or only by the host interrupt enable bit.
16.3.13 Host Interface Select Register (HISEL) HISEL selects the function of bits 7 to 4 in the STR3 register. In addition, this register selects the output of host interrupt request signal of each frame. R/W Bit Bit Name Initial Value Slave Host Description 7 SELSTR3 0 R/W STR3 Register Function Select 3 Sets the functions of bits 7 to 4 in STR3 together with the TWRE bit in LADR3L. For details see section 16.3.9, Status Register 1 to 3 (STR1 to STR3).
16.3.14 SMIC Flag Register (SMICFLG) SMICFLG is one of the registers used to implement SMIC mode. This register includes bits that indicate whether or not the system is ready to data transfer and those that are used for handshake of the transfer cycles. R/W Bit Bit Name Initial Value Slave Host Description 7 RX_DATA_ 0 RDY R/W R Read Transfer Ready Indicates whether or not the slave is ready for the host read transfer.
R/W Bit Bit Name Initial Value Slave Host Description 3 SEVT_ ATN 0 R/W R Event Flag When the slave detects an event for the host, this bit is set. 0: Indicates waiting for event detection 1: Indicates event detection 2 SMS_ ATN 0 R/W R SMS Flag When there is a message to be transmitted from the slave to the host, this bit is set. 0: There is not a message 1: There is a message 1 0 R/W R Reserved The initial value should not be changed.
16.3.15 SMIC Control Status Register (SMICCSR) SMICCSR is one of the registers used to implement SMIC mode. This is an 8-bit readable/writable register that stores a control code issued from the host and a status code that is returned from the slave. The control code is written to this register accompanied by the transfer between the host and slave. The status code is returned to this register to indicate that the slave has recognized the control code, and a specified transfer cycle has been completed. 16.
R/W Bit Bit Name Initial Value Slave Host Description 7 to 5 All 0 R/W Reserved The initial value should not be changed. 4 HDTWI 0 R/(W)* Transfer Data Transmission End Interrupt This is a status flag that indicates that the host has finished transmitting the transfer data to SMICDTR. When the IBFIE3 bit and HDTWIE bit are set to 1, the IBFI3 interrupt is requested to the slave.
R/W Bit Bit Name Initial Value Slave Host Description 1 CTLWI 0 R/(W)* Control Code Transmission End Interrupt This is a status flag that indicates that the host has finished transmitting the control code to SMICCSR. When the IBFIE3 bit and CTLWIE bit are set to1, the IBFI3 interrupt is requested to the slave. 0: Control code transmission wait state [Clearing condition] After the slave reads CTLWI = 1, writes 0 to this bit.
16.3.18 SMIC Interrupt Register 1 (SMICIR1) SMICIR1 is one of the registers used to implement SMIC mode. This register includes the bits that enables/disables an interrupt to the slave. The IBFI3 interrupt is enabled by setting the IBFIE3 bit in HICR2 to 1. R/W Bit Bit Name Initial Value Slave Host Description 7 to 5 4 All 0 HDTWIE 0 R/W Reserved The initial value should not be changed.
16.3.19 BT Status Register 0 (BTSR0) BTSR0 is one of the registers used to implement BT mode. This register includes flags that control interrupts to the slave (this LSI). R/W Bit Bit Name Initial Value Slave Host Description 7 to 5 All 0 R/W 4 0 R/(W)* Reserved The initial value should not be changed. FRDI FIFO Read Request Interrupt This status flag indicates that host writes the data to BTDTR buffer with FIFO full state at the host write transfer.
R/W Bit Bit Name Initial Value Slave Host Description 2 HWRI 0 R/(W)* BT Host Write Interrupt This status flag indicates that the host writes 1byte to BTDTR buffer. When the IBFIE3 bit and HWRIE bit are set to 1, IBFI3 interrupt is requested to the slave. 0: Host BTDTR write wait state [Clearing condition] After the slave reads HWRI = 1, writes 0 to this bit. 1: The host writes to BTDTR [Setting condition] The host writes one byte to BTDTR.
16.3.20 BT Status Register 1 (BTSR1) BTSR1 is one of the registers used to implement the BT mode. This register includes a flag that controls an interrupt to the slave (this LSI). R/W Bit Bit Name Initial Value Slave Host Description 7 0 R/W 6 HRSTI 0 R/(W)* Reserved The initial value should not be changed. BT Reset Interrupt This status flag indicates that the BMC_HWRST bit in BTIMSR is set to 1 by the host.
R/W Bit Bit Name Initial Value Slave Host Description 4 BEVTI 0 R/(W)* BEVT_ATN Clear Interrupt This status flag indicates that the BEVT_ATN bit in BTCR is cleared by the host. When the IBFIE3 bit and BEVTIE bit are set to 1, IBFI3 interrupt is requested to the slave. 0: [Clearing condition] When the slave reads BEVTI = 1 and writes 0 to this bit. 1: [Setting condition] When the slave detects the falling edge of BEVT_ATN.
R/W Bit Bit Name Initial Value Slave Host Description 1 CRRPI 0 R/(W)* Read Pointer Clear Interrupt This status flag indicates that the CLR_RD_PTR bit in BTCR is set to 1 by the host. When the IBFIE3 bit and CRRPIE bit are set to 1, the IBFI3 interrupt is requested to the slave. 0: [Clearing condition] After the slave reads CRRPI = 1, writes 0 to this bit. 1: [Setting condition] When the slave detects the rising edge of CLR_RD_PTR.
16.3.21 BT Control Status Register 0 (BTCSR0) BTCSR0 is one of the registers used to implement the BT mode. The BTCSR0 register contains the bits used to switch FIFOs in BT transfer, and enable or disable the interrupts to the slave (this LSI). The IBFI3 interrupt is enabled by setting the IBFIE3 bit in HICR2 to 1. R/W Bit Bit Name Initial Value Slave Host Description 7 0 R/W Reserved The initial value should not be changed.
R/W Bit Bit Name Initial Value Slave Host Description 1 HBTWIE 0 R/W BTDTR Host Write Start Interrupt Enable Enables or disables the HBTWI interrupt which is an IBFI3 interrupt source to the slave. 0: BTDTR host write start interrupt is disabled. 1: BTDTR host write start interrupt is enabled. 0 HBTRIE 0 R/W BTDTR Host Read End Interrupt Enable Enables or disables the HBTRI interrupt which is an IBFI3 interrupt source to the slave. 0: BTDTR host read end interrupt is disabled.
R/W Bit Bit Name Initial Value Slave Host Description 4 0 BEVTIE R/W BEVT_ATN Clear Interrupt Enable Enables or disables the BEVTI interrupt which is an IBFI3 interrupt source to the slave. 0: BEVT_ATN clear interrupt is disabled. 1: BEVT_ATN clear interrupt is enabled. 3 B2HIE 0 R/W Read End Interrupt Enable Enables or disables the B2HI interrupt which is an IBFI3 interrupt source to the slave. 0: Read end interrupt is disabled. 1: Read end interrupt is enabled.
16.3.23 BT Control Register (BTCR) BTCR is one of the registers used to implement BT mode. The BTCR register contains bits used in transfer cycle handshaking, and those indicating the completion of data transfer to the buffer. R/W Bit Bit Name Initial Value Slave Host 7 1 B_BUSY R/W R Description BT Write Transfer Busy Flag Read-only bit from the host. Indicates that the BTDTR buffer is being used for BT write transfer (write transfer is in progress.
R/W Bit Bit Name 4 Initial Value Slave BEVT_ATN 0 Host 1 Description 5 R/(W)* R/(W)* Event Interrupt Sets when the slave detects an event to the host. Setting the B2H_IRQ_EN bit in the BTIMSR register enables the BEVT_ATN bit to be used as an interrupt source to the host. 0: No event interrupt request is available [Clearing condition] When the host writes a 1 to the bit. 1: An event interrupt request is available [Setting condition] When the slave writes a 1 after a 0 has been read from BEVT_ATN.
R/W Bit Bit Name 1 Initial Value CLR_RD_ 0 PTR Slave Host Description 2 R/(W)* (W)*1 Read Pointer Clear This bit is used by the host to clear the read pointer during read transfer. A host read operation always yields 0 on readout. 0: Read pointer clear wait [Clearing condition] When the slave writes a 0 after a 1 has been read from CLR_RD_PTR. 1: Read pointer clear [Setting condition] When the host writes a 1.
16.3.24 BT Data Buffer (BTDTR) BTDTR is used to implement the BT mode. BTDTR consists of two FIFOs: the host write transfer FIFO and the host read transfer FIFO. Their capacities are 64 bytes each. When using BTDTR, enable FIFO by means of the bits FSEL0 and FSEL1. R/W Bit Bit Name Initial Value Slave Host 7 to bit7 to bit0 Undefined 0 R/W R/W Description The data written by the host is stored in FIFO (64 bytes) for host write transfer and read out by the slave in order of host writing.
16.3.25 BT Interrupt Mask Register (BTIMSR) BTIMSR is one of the registers used to implement BT mode. The BTIMSR register contains the bits used to control the interrupts to the host. R/W Bit Bit Name 7 BMC_ HWRST Initial Value Slave 0 Host 2 Description 1 R/(W)* R/(W)* Slave Reset Performs a reset from the host to the slave. The host can only write a 1. Writing a 0 to this bit is invalid. The host will always return a 0 on read out. Setting the RSTRENBL bit enables a 1 to be read from the host.
R/W Bit Bit Name 1 B2H_IRQ Initial Value Slave 0 Host 1 Description 3 R/(W)* R/(W)* BMC to HOST interrupt Informs the host that an interrupt has been requested when the BEVT_ATN or B2H_ATN bit has been set. The SERIRQ is not issued. To generate the SERIRQ, it should be issued by the program. 0: B2H_IRQ interrupt is not requested [Clearing condition] When the host writes a 1.
16.3.26 BT FIFO Valid Size Register 0 (BTFVSR0) BTFVSR0 is one of the registers used to implement BT mode. BTFVSR0 indicates a valid data size in the FIFO for host write transfer. R/W Bit Bit Name Initial Value Slave Host Description 7 to 0 N7 to N0 All 0 R These bits indicate the number of valid bytes in the FIFO (the number of bytes which the slave can read) for host write transfer.
16.4 Operation 16.4.1 LPC Interface Activation The LPC interface is activated by setting at least one of bits LPC3E to LPC1E (bits 7 to 5) in HICR0 to 1. When the LPC interface is activated, the related I/O ports (PE7 to PE0, PD5, and PD4) function as dedicated LPC interface input/output pins. In addition, setting the FGA20E, PMEE, LSMIE, and LSCIE bits to 1 adds the related I/O ports (ports PD3 to PD0) to the LPC interface's input/output pins.
If the received address matches the host address in an LPC register, the LPC interface enters the busy state; it returns to the idle state by output of a state #12 turnaround. Register (IDR, etc.) and flag (IBF, etc.) changes are made at this timing, so in the event of a transfer cycle forced termination (abort) before state #12, registers and flags are not changed. Table 16.
The timing of the LFRAME, LCLK, and LAD signals is shown in figures 16.2 and 16.3. LCLK LFRAME LAD3 to LAD0 Start ADDR TAR Sync Data TAR Start Cycle type, direction, and size Number of clocks 1 1 4 2 1 2 2 1 Figure 16.2 Typical LFRAME Timing LCLK LFRAME LAD3 to LAD0 Start ADDR Cycle type, direction, and size TAR Sync Slave must stop driving Master will drive high Too many Syncs cause timeout Figure 16.3 Abort Mechanism 16.4.3 SMIC Mode Transfer Flow Figure 16.
Slave Host Wait for BUSY = 0 Host confirms the BUSY bit in SMICFLG. The bit indicates slave (this LSI) is ready for receiving a new control code. When BUSY = 1, access from host is disabled. Bit that indicates slave is ready for write transfer. Issues when slave is ready for the next write transfer. Wait for TX_DATA_RDY = 1 Host confirms the TX_DATA_RDY bit in SMICFLG. The confirmation is unnecessary when Write Start control is issued.
Slave Host Wait for BUSY = 0 Bit that indicates slave is ready for read transfer. Issues when slave is ready for the next read transfer. Slave waits for the BUSY bit in SMICFLG is set. Waits for RX_DATA_RDY = 1 A Write control code Slave confirms that control code is written to SMICCSR by host. The CTLWI bit in SMICIR0 is set. Host confirms the BUSY bit in SMICFLG. The bit indicates slave (this LSI) is ready for receiving a new control code. When BUSY = 1, access from host is disabled.
16.4.4 BT Mode Transfer Flow Figure 16.6 shows the write transfer flow and figure 16.7 shows the read transfer flow in BT mode. Slave Host Slave waits for the H2B_ATN bit (interrupt from host) is set. Wait for B_BUSY = 0 Host confirms the B_BUSY bit in BTCR. Wait for H2B_ATN = 0 Host confirms the H2B_ATN bit in BTCR. Clear write pointer Confirms the CLR_WR_PTR bit. The CRWPI bit in BTSR1 is set to notify write pointer clearing as an interrupt to slave.
Slave Host Slave confirms the H_BUSY bit in BTCR. Slave writes data of 1 to n bytes to the BTDTR buffer. Slave sets the B2H_ATN bit in BTCR to indicate data write completion to the BTDTR buffer. Wait for H_BUSY = 0 Write BTDTR buffer B2H_ATN = 1 Generate host interrupt H_BUSY = 1 Clear read pointer Confirms the CLR_RD_PTR bit. The CRRPI bit in BTSR1 is set to notify read pointer clearing as an interrupt source to slave. Host sets the H_BUSY bit in BTCR.
16.4.5 A20 Gate The A20 gate signal can mask address A20 to emulate an addressing mode used by personal computers with an 8086-family CPU*. A regular-speed A20 gate signal can be output under firmware control. The fast A20 gate function that is speeded up by the hardware is enabled by setting the FGA20E bit to 1 in HICR0. Note: * An Intel microcomputer Regular A20 Gate Operation: Output of the A20 gate signal can be controlled by an H'D1 command followed by data.
Start Host write No H'D1 command received? Yes Wait for next byte Host write No Data byte? Yes Write bit 1 of data byte to DR bit of PD3/GA20 Figure 16.8 GA20 Output Rev. 3.
Table 16.
16.4.6 LPC Interface Shutdown Function (LPCPD) The LPC interface can be placed in the shutdown state according to the state of the LPCPD pin. There are two kinds of LPC interface shutdown state: LPC hardware shutdown and LPC software shutdown. The LPC hardware shutdown state is controlled by the LPCPD pin, while the LPC software shutdown state is controlled by the SDWNB bit.
Table 16.
Table 16.
Notes: System reset: Reset by STBY input, RES input, or WDT overflow LPC reset: Reset by LPC hardware reset (HR) or LPC software reset (SR) LPC shutdown: Reset by LPC hardware shutdown (HS) or LPC software shutdown (SS) Figure 16.9 shows the timing of the LPCPD and LRESET signals. LCLK LPCPD LAD3 to LAD0 LFRAME At least 30 µs At least 100 µs At least 60 µs LRESET Figure 16.9 Power-Down State Termination Timing Rev. 3.
16.4.7 LPC Interface Serialized Interrupt Operation (SERIRQ) A host interrupt request can be issued from the LPC interface by means of the SERIRQ pin. In a host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the serialized interrupt transfer cycle generated by the host or a supporting function, and a request signal is generated by the frame corresponding to that interrupt. The timing is shown in figure 16.10.
Table 16.
clock must first be issued to the host. For details see section 16.4.8, LPC Interface Clock Start Request. 16.4.8 LPC Interface Clock Start Request A request to restart the clock (LCLK) can be sent to the host processor by means of the CLKRUN pin. With LPC data transfer and SERIRQ in continuous mode, a clock restart is never requested since the transfer cycles are initiated by the host.
16.5 Interrupt Sources 16.5.1 IBFI1, IBFI2, IBFI3, ERRI The LPC interface has four interrupt requests to the slave processor: IBFI1, IBFI2, IBFI3, and ERRI. IBFI1 and IBFI2 are receive complete interrupts for IDR1 and IDR2 respectively. IBFI3 is a receive complete interrupt for IDR3 and TWR, and the interrupt in SMIC mode and BT mode. The ERRI interrupt indicates the occurrence of a special state, such as an LPC reset, LPC shutdown, or transfer cycle abort.
set to 1. In order to clear a host interrupt request, it is necessary to clear the host interrupt enable bit. Table 16.12 summarizes the methods of setting and clearing these bits, and figure 16.12 shows the processing flowchart. Table 16.
Slave CPU Master CPU ODR1 write Write 1 to IRQ1E1 No SERIRQ IRQ1 output Interrupt initiation SERIRQ IRQ1 source clearance ODR1 read OBF1 = 0? Yes No All bytes transferred? Hardware operation Yes Software operation Figure 16.12 HIRQ Flowchart (Example of Channel 1) Rev. 3.
16.6 16.6.1 Usage Notes Module Stop Setting The LPC operation stop or enable can be specified by the module stop control register. With the initial value, LPC operation will stop. Releasing module stop mode enables access to the register. For details see section 23, Power-Down Modes. 16.6.
Table 16.
Section 17 D/A Converter 17.1 • • • • • Features 8-bit resolution Two output channels Conversion time: Max. 10 µs (when load capacitance is 20 pF) Output voltage: 0 V to AVref D/A output retaining function in software standby mode Internal data bus Bus interface Module data bus AVref AVCC DA1 8-bit D/A D A D R 0 D A D R 1 D A C R DA0 AVSS Control circuit [Legend] DACR: D/A control register DADR0: D/A data register 0 DADR1: D/A data register 1 Figure 17.
17.2 Input/Output Pins Table 17.1 summarizes the input/output pins used by the D/A converter. Table 17.1 Pin Configuration Pin Name Symbol I/O Function Analog power supply pin AVCC Input Analog block power supply Analog ground pin AVSS Input Analog block ground and reference voltage Analog output pin 0 DA0 Output Channel 0 analog output Analog output pin 1 DA1 Output Channel 1 analog output Input Analog block reference voltage Reference power supply pin AVref Rev. 3.
17.3 Register Descriptions The D/A converter has the following registers. • D/A data register 0 (DADR0) • D/A data register 1 (DADR1) • D/A control register (DACR) 17.3.1 D/A Data Registers 0 and 1 (DADR0, DADR1) DADR0 and DADR1 are 8-bit readable/writable registers that store data for D/A conversion. When analog output is permitted, D/A data register contents are converted and output to analog output pins. 17.3.2 D/A Control Register (DACR) DACR controls D/A converter operation.
Table 17.2 D/A Channel Enable Bit 7 Bit 6 Bit 5 DAOE1 DAOE0 DAE Description 0 0 * Disables D/A conversion 1 0 Enables D/A conversion for channel 0 Disables D/A conversion for channel 1 1 0 1 Enables D/A conversion for channels 0 and 1 0 Disables D/A conversion for channel 0 Enables D/A conversion for channel 1 1 1 Enables D/A conversion for channels 0 and 1 * Enables D/A conversion for channels 0 and 1 [Legend] *: Don't care Rev. 3.
17.4 Operation The D/A converter incorporates two channels of the D/A circuits and can be converted individually. When the DAOE bit in DACR is set to 1, D/A conversion is enabled and conversion results are output. An example of D/A conversion of channel 0 is shown below. The operation timing is shown in figure 17.2. 1. Write conversion data to DADR0. 2. When the DAOE0 bit in DACR is set to 1, D/A conversion starts. After the interval of tDCONV, conversion results are output from the analog output pin DA0.
17.5 Usage Note When this LSI enters software standby mode with D/A conversion enabled, the D/A output is retained, and the analog power supply current is equal to as during D/A conversion. If the analog power supply current needs to be reduced in software standby mode, clear the DAOE1, DAOE0, and DAE bits all to 0 to disable D/A output. Rev. 3.
Section 18 A/D Converter This LSI includes a successive-approximation-type 10-bit A/D converter that allows up to eight analog input channels to be selected. 18.1 Features • 10-bit resolution • Input channels: eight analog input channels • Analog conversion voltage range can be specified using the reference power supply voltage pin (AVref) as an analog reference voltage. • Conversion time: 8.
18.1.1 Block Diagram A block diagram of the A/D converter is shown in figure 18.1.
18.2 Input/Output Pins Table 18.1 summarizes the pins used by the A/D converter. The 8 analog input pins are divided into two groups consisting of four channels. Analog input pins 0 to 3 (AN0 to AN3) comprising group 0 and analog input pins 4 to 7 (AN4 to AN7) comprising group1. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. Table 18.
18.3 Register Descriptions The A/D converter has the following registers. • • • • • • A/D data register A (ADDRA) A/D data register B (ADDRB) A/D data register C (ADDRC) A/D data register D (ADDRD) A/D control/status register (ADCSR) A/D control register (ADCR) 18.3.1 A/D Data Registers A to D (ADDRA to ADDRD) There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion.
18.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D conversion operations. Bit Bit Name Initial Value R/W Description 7 ADF 0 R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion.
Bit Bit Name Initial Value R/W Description 2 1 0 CH2 CH1 CH0 All 0 R/W Channel Select 2 to 0 Note: * 18.3.3 Select analog input channels. When SCAN = 0 When SCAN = 1 000: AN0 000: AN0 001: AN1 001: AN0 and AN1 010: AN2 010: AN0 to AN2 011: AN3 011: AN0 to AN3 100: AN4 100: AN4 101: AN5 101: AN4 and AN5 110: AN6 110: AN4 to AN6 111: AN7 111: AN4 to AN7 Only 0 can be written for clearing the flag.
18.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 18.4.
18.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) passes after the ADST bit in ADCSR is set to 1, then starts A/D conversion. Figure 18.2 shows the A/D conversion timing. Table 18.3 indicates the A/D conversion time. As indicated in figure 18.2, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL).
Table 18.3 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1* Item Symbol min typ max min typ max A/D conversion start delay time tD 10 17 6 9 Input sampling time tSPL 63 31 A/D conversion time tCONV 259 266 131 134 Notes: Values in the table indicate the number of states. * in the table indicates that the system clock (φ) is 16 MHz or lower. 18.4.4 External Trigger Input Timing A/D conversion can be externally triggered.
18.5 Interrupt Source The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 enables ADI interrupt requests while the ADF bit in ADCSR is set to 1 after A/D conversion ends. The ADI interrupt can be used as a DTC activation interrupt source. Table 18.4 A/D Converter Interrupt Source Name Interrupt Source Interrupt Flag DTC Activation ADI A/D conversion end ADF Possible 18.
Digital output Ideal A/D conversion characteristic 111 110 101 100 011 010 Quantization error 001 000 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 18.4 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 18.5 A/D Conversion Accuracy Definitions Rev. 3.
18.7 Usage Notes 18.7.1 Permissible Signal Source Impedance This LSI’s analog input is designed so that the conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less. This specification is provided to enable the A/D converter’s sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 kΩ, charging may be insufficient and it may not be possible to guarantee the A/D conversion accuracy.
18.7.3 Setting Range of Analog Power Supply and Other Pins If conditions shown below are not met, the reliability of this LSI may be adversely affected. • Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVSS ≤ ANn ≤ AVref (n = 0 to 7). • Relation between AVCC, AVSS and VCC, VSS For the relationship between AVCC, AVSS and VCC, VSS, set AVSS = VSS, and AVCC = VCC is not always necessary.
AVCC AVref *1 Rin *2 *1 100 Ω AN0 to AN7 0.1 µF AVSS Notes: Values are reference values. *1 10 µF *2 0.01 µF Rin: Input impedance Figure 18.7 Example of Analog Input Protection Circuit 10 kΩ To A/D converter AN0 to AN7 20 pF Note: Values are reference values. Figure 18.8 Analog Input Pin Equivalent Circuit Rev. 3.
Section 19 RAM This LSI has 40 kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on SYSCR, see section 3.2.2, System Control Register (SYSCR). Rev. 3.
Rev. 3.
Section 20 Flash Memory (0.18-µm F-ZTAT Version) The flash memory has the following features. Figure 20.1 shows a block diagram of the flash memory. 20.
User boot mode The user boot program of the optional interface can be made and the user MAT can be programmed. • Programming/erasing protection Sets protection against flash memory programming/erasing via hardware, software, or error protection. • Programmer mode This mode uses the PROM programmer. The user MAT and user boot MAT can be programmed.
20.1.1 Operating Mode When each mode pin and the FWE pin are set in the reset state and reset start is performed, this LSI enters each operating mode as shown in figure 20.2. • Flash memory can be read in user mode, but cannot be programmed or erased. • Flash memory can be read, programmed, or erased on the board only in boot mode, user program mode, and user boot mode. • Flash memory can be read, programmed, or erased by means of the PROM programmer in programmer mode.
20.1.2 Mode Comparison The comparison table of programming and erasing related items about boot mode, user program mode, user boot mode, and programmer mode is shown in table 20.1. Table 20.
20.1.3 Flash Memory MAT Configuration This LSI’s flash memory is configured by the 8-kbyte user boot MAT and 256-kbyte (H8S/2168), 384-kbyte (H8S/2167), or 512-kbytes (H8S/2166) user MAT. The start address is allocated to the same address in the user MAT and user boot MAT. Therefore, when the program execution or data access is performed between two MATs, the MAT must be switched by using FMATS. The user MAT or user boot MAT can be read in all modes.
20.1.4 Block Division The user MAT is divided into 64 kbytes (three blocks for H8S/2168, five blocks for H8S/2167, seven blocks for H8S/2166), 32 kbytes (one block), and 4 kbytes (eight blocks) as shown in figure 20.4. The user MAT can be erased in this divided-block units and the erase-block number of EB0 to EB15 is specified when erasing. Rev. 3.
EB0 →Programming unit: 128 bytes→ H'00007F H'000F82 – – – – – – – – – – – – – – H'000FFF H'001002 →Programming unit: 128 bytes→ H'00107F H'001F82 – – – – – – – – – – – – – – H'001FFF H'002002 →Programming unit: 128 bytes→ H'00207F H'002F82 – – – – – – – – – – – – – – H'002FFF H'003002 →Programming unit: 128 bytes→ H'00307F H'003F82 – – – – – – – – – – – – – – H'003FFF H'004002 →Programming unit: 128 bytes→ H'00407F H'00BF82 – – – – – – – – – – – – – – H'00BFFF H'00C002 →Progra
20.1.5 Programming/Erasing Interface Programming/erasing is executed by downloading the on-chip program to the on-chip RAM and specifying the program address/data and erase block by using the interface register/parameter. The procedure program is made by the user in user program mode and user boot mode. An overview of the procedure is given as follows. For details, see section 20.4.2, User Program Mode. Start user procedure program for programming/erasing.
2. Download of on-chip program The on-chip program is automatically downloaded by setting the flash key code register (FKEY) and the SCO bit in the flash code control status register (FCCS), which are programming/erasing interface registers. The flash memory is replaced to the embedded program storage area when downloading.
20.2 Input/Output Pins Table 20.2 shows the flash memory pin configuration. Table 20.2 Pin Configuration Pin Name Input/Output Function RES Input Reset FWE Input Flash memory programming/erasing enable pin MD2 Input Sets operating mode of this LSI MD1 Input Sets operating mode of this LSI MD0 Input Sets operating mode of this LSI TxD1 Output Serial transmit data output (used in boot mode) RxD1 Input Serial receive data input (used in boot mode) 20.
Table 20.3 Register/Parameter and Target Mode Download Programming/ FCCS Erasing Interface FPCS Register FECS FTDAR Programming/ DPFR Erasing Interface FPFR Parameter FPEFEQ Programming Erasure Read FKEY FMATS Initialization *1 *1 *2 FMPAR FMPDR FEBS Notes: 1. The setting is required when programming or erasing user MAT in user boot mode. 2.
• Flash Code Control Status Register (FCCS) FCCS is configured by bits which request the monitor of the FWE pin state and error occurrence during programming or erasing flash memory and the download of on-chip program. Bit Initial Bit Name Value R/W Description 7 FWE R Flash Program Enable 1/0 Monitors the signal level input to the FWE pin and enables or disables programming/erasing flash memory.
Bit Initial Bit Name Value R/W Description 3 WEINTE R/W Program/Erase Enable 0 Modifies the space for the interrupt vector table, when interrupt vector data is not read successfully during programming/erasing flash memory or switching between a user MAT and a user boot MAT. When this bit is set to 1, interrupt vector data is read from address spaces H'FFE080 to H'FFE0FF (on-chip RAM space), instead of from address spaces H'000000 to H'00007F (up to vector number 31).
Bit Initial Bit Name Value R/W Description 0 SCO (R)/W* [Clearing condition] When download is completed 0 1: Request that the on-chip programming/erasing program is downloaded to the on-chip RAM is occurred. [Setting conditions] When all of the following conditions are satisfied and 1 is set to this bit • H'A5 is written to FKEY • Note: * During execution in the on-chip RAM This bit is a write only bit. This bit is always read as 0.
• Flash Key Code Register (FKEY) FKEY is a register for software protection that enables download of on-chip program and programming/erasing of flash memory. Before setting the SCO bit to 1 in order to download onchip program or executing the downloaded programming/erasing program, these processing cannot be executed if the key code is not written.
• Flash MAT Select Register (FMATS) FMATS specifies whether user MAT or user boot MAT is selected. Bit Initial Bit Name Value R/W Description 7 6 5 4 3 2 1 0 MS7 MS6 MS5 MS4 MS3 MS2 MS1 MS0 R/W R/W R/W R/W R/W R/W R/W R/W MAT Select 0/1* 0 0/1* 0 0/1* 0 0/1* 0 These bits are in user-MAT selection state when the value other than H'AA is written and in user-boot-MAT selection state when H'AA is written. The MAT is switched by writing the value in FMATS. When the MAT is switched, follow section 20.
• Flash Transfer Destination Address Register (FTDAR) FTDAR is a register that specifies the address to download an on-chip program. This register must be specified before setting the SCO bit in FCCS to 1. Bit Initial Bit Name Value R/W Description 7 TDER R/W Transfer Destination Address Setting Error 0 This bit is set to 1 when the address specified by bits TDA6 to TDA0, which is the start address to download an on-chip program, is over the range.
20.3.2 Programming/Erasing Interface Parameter The programming/erasing interface parameter specifies the operating frequency, storage place for program data, programming destination address, and erase block and exchanges the processing result for the downloaded on-chip program. This parameter uses the general registers of the CPU (ER0 and ER1) or the on-chip RAM area. The initial value is undefined at a reset or in hardware standby mode.
Table 20.
(1) Download Control The on-chip program is automatically downloaded by setting the SCO bit to 1. The on-chip RAM area to be downloaded is the 2-kbyte area starting from the address specified by FTDAR. Download control is set by the program/erase interface registers, and the DPFR parameter indicates the return value. (a) Download pass/fail result parameter (DPFR: single byte of start address specified by FTDAR) This parameter indicates the return value of the download result.
(2) Programming/Erasing Initialization The on-chip programming/erasing program to be downloaded includes the initialization program. The specified period pulse must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. The operating frequency of the CPU must be set. The initial program is set as a parameter of the programming/erasing program which has downloaded these settings.
(b) Flash pass/fail parameter (FPFR: general register R0L of CPU) This parameter indicates the return value of the initialization result. Bit Initial Bit Name Value R/W Description 7 to 2 Unused Return 0 1 FQ R/W Frequency Error Detect Returns the check result whether the specified operating frequency of the CPU is in the range of the supported operating frequency.
(a) Flash multipurpose address area parameter (FMPAR: general register ER1 of CPU) This parameter stores the start address of the programming destination on the user MAT. When the address in the area other than flash memory space is set, an error occurs. The start address of the programming destination must be at the 128-byte boundary. If this boundary condition is not satisfied, an error occurs. The error occurrence is indicated by the WA bit (bit 1) in FPFR.
Bit Initial Bit Name Value 6 MD R/W Description R/W Programming Mode Related Setting Error Detect Returns the check result that a high level signal is input to the FWE pin and the error protection state is not entered. When the low level signal is input to the FWE pin or the error protection state is entered, 1 is written to this bit. The state can be confirmed with the FWE and FLER bits in FCCS. For conditions to enter the error protection state, see section 20.5.3, Error Protection.
Bit Initial Bit Name Value 1 WA R/W Description R/W Write Address Error Detect When the following items are specified as the start address of the programming destination, an error occurs. • When the programming destination address in the area other than flash memory is specified • When the specified address is not in a 128-byte boundary. (The lower eight bits of the address are other than H'00 and H'80.
(4) Erasure Execution When flash memory is erased, the erase-block number on the user MAT must be passed to the erasing program which is downloaded. This is set to the FEBS parameter (general register ER0). One block is specified from the block number 0 to 15. For details on the erasing processing procedure, see section 20.4.2, User Program Mode. (a) Flash erase block select parameter (FEBS: general register ER0 of CPU) This parameter specifies the erase-block number.
(b) Flash pass/fail parameter (FPFR: general register R0L of CPU) This parameter returns value of the erasing processing result. Bit Initial Bit Name Value R/W Description 7 Unused 6 MD R/W Programming Mode Related Setting Error Detect Return 0. Returns the check result that a high level signal is input to the FWE pin and the error protection state is not entered. When the low level signal is input to the FWE pin or the error protection state is entered, 1 is written to this bit.
Bit Initial Bit Name Value R/W Description 2, 1 Unused Return 0. 0 SF R/W Success/Fail Indicates whether the erasing processing is ended normally or not. 0: Erasure is ended normally (no error) 1: Erasure is ended abnormally (error occurs) 20.4 On-Board Programming Mode When the pin is set in on-board programming mode and the reset start is executed, the on-board programming state that can program/erase the on-chip flash memory is entered.
The system configuration diagram in boot mode is shown in figure 20.6. For details on the pin setting in boot mode, see table 20.5. The NMI and other interrupts are ignored in boot mode. However, the NMI and other interrupts should be disabled in the user system. This LSI Host Boot Control command, program data programming tool and program data Reply response Control command, analysis execution software (on-chip) Flash memory RxD1 On-chip SCI_1 TxD1 On-chip RAM Figure 20.
Table 20.6 System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI Bit Rate of Host System Clock Frequency 4,800 bps 5 to 33 MHz 9,600 bps 5 to 33 MHz 19,200 bps 8 to 33 MHz (2) State Transition Diagram The overview of the state transition diagram after boot mode is initiated is shown in figure 20.8. 1. Bit rate adjustment After boot mode is initiated, the bit rate of the SCI interface is adjusted with that of the host. 2.
(Bit rate adjustment) H'00.......H'00 reception H'00 transmission (adjustment completed) Boot mode initiation (reset by boot mode) Bit rate adjustment H'55 2. ption rece Inquiry command reception Wait for inquiry setting command Inquiry command response 3. 4. 1.
20.4.2 User Program Mode The user MAT can be programmed/erased in user program mode. (The user boot MAT cannot be programmed/erased.) Programming/erasing is executed by downloading the program in the microcomputer. The overview flow is shown in figure 20.9. High voltage is applied to internal flash memory during the programming/erasing processing. Therefore, transition to reset or hardware standby must not be executed. Doing so may damage or destroy flash memory.
(1) On-chip RAM Address Map when Programming/Erasing is Executed Parts of the procedure program that are made by the user, like download request, programming/erasing procedure, and determination of the result, must be executed in the on-chip RAM. The on-chip program that is to be downloaded is all in the on-chip RAM. Note that area in the on-chip RAM must be controlled so that these parts do not overlap. Figure 20.10 shows the program area to be downloaded.
(2) Programming Procedure in User Program Mode The procedures for download, initialization, and programming are shown in figure 20.11. 1. Disable interrupts and bus master operation other than CPU Set FKEY to H'A5 2. Set FKEY to H'5A 10. Set SCO to 1 and execute download 3. Set parameters to ER1 and ER0 (FMPAR and FMPDR) 11. Clear FKEY to 0 4. Programming JSR FTDAR setting + 16 12. 5.
128-byte programming is performed in one program processing. When more than 128-byte programming is performed, programming destination address/program data parameter is updated in 128-byte units and programming is repeated. When less than 128-byte programming is performed, data must total 128 bytes by adding the invalid data. If the dummy data to be added is H'FF, the program processing period can be shortened. 1.
In the download processing, any interrupts are not accepted. However, interrupt requests are held. Therefore, when the user procedure program is returned, the interrupts occur. When the level-detection interrupt requests are to be held, interrupts must be input until the download is ended. When hardware standby mode is entered during download processing, the normal download cannot be guaranteed in the on-chip RAM. Therefore, download must be executed again.
MOV.L #DLTOP+32,ER2 ; Set entry address to ER2 JSR NOP @ER2 ; Call initialization routine The general registers other than R0L are held in the initialization program. R0L is a return value of the FPFR parameter. Since the stack area is used in the initialization program, 128-byte stack area at the maximum must be allocated in RAM. Interrupts can be accepted during the execution of the initialization program.
Example of the FMPDR setting When the storage destination of the program data is flash memory, even if the program execution routine is executed, programming is not executed and an error is returned to the FPFR parameter. In this case, the program data must be transferred to the on-chip RAM and then programming must be executed. 12. Programming There is an entry point of the programming program in the area from the start address specified by FTDAR + 16 bytes of the on-chip RAM.
(3) Erasing Procedure in User Program Mode The procedures for download, initialization, and erasing are shown in figure 20.12. Start erasing procedure program 1 Set FKEY to H'A5 Set FKEY to H'5A Set SCO to 1 and execute download Set FEBS parameter 2. Erasing JSR FTDAR setting + 16 3. Clear FKEY to 0 DPFR = 0? Yes 4. FPFR = 0 ? No Yes Download error processing Set the FPEFEQ parameter Initialization Disable interrupts and bus master operation other than CPU 1.
1. Select the on-chip program to be downloaded Set the EPVB bit in FECS to 1. Several programming/erasing programs cannot be selected at one time. If several programs are set, download is not performed and a download error is reported to the SS bit in the DPFR parameter. Specify the start address of a download destination by FTDAR. The procedures to be carried out after setting FKEY, e.g. download and initialization, are the same as those in the programming procedure.
(4) Erasing and Programming Procedure in User Program Mode By changing the on-chip RAM address of the download destination in FTDAR, the erasing program and programming program can be downloaded to separate on-chip RAM areas. Figure 20.13 shows a repeating procedure of erasing and programming.
20.4.3 User Boot Mode This LSI has user boot mode which is initiated with different mode pin settings than those in boot mode or user program mode. User boot mode is a user-arbitrary boot mode, unlike boot mode that uses the on-chip SCI. Only the user MAT can be programmed/erased in user boot mode. Programming/erasing of the user boot MAT is only enabled in boot mode or programmer mode. (1) User Boot Mode Initiation For the mode pin settings to start up user boot mode, see table 20.5.
Start programming procedure program 1 Select on-chip program to be downloaded and specify download destination by FTDAR Set FMATS to value other than H'AA to select user MAT MAT switchover Yes No Download error processing Set the FPEFEQ parameters Initialization JSR FTDAR setting + 32 FPFR = 0 ? Set parameter to ER0 and ER1 (FMPAR and FMPDR) Programming Clear FKEY to 0 User-MAT selection state Download Set FKEY to H'A5 Set SCO to 1 and execute download DPFR = 0 ? Initialization User-boot-M
Except for MAT switching, the programming procedure is the same as that in user program mode. The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 20.4.4, Procedure Program and Storable Area for Programming Data.
The difference between the erasing procedures in user program mode and user boot mode depends on whether the MAT is switched or not as shown in figure 20.15. MAT switching is enabled by writing a specific value to FMATS. However note that while the MATs are being switched, the LSI is in an unstable state, e.g. access to a MAT is not allowed until MAT switching is completed, and if an interrupt occurs, from which MAT the interrupt vector is read is undetermined.
Transitions to the reset state, and hardware standby mode are inhibited during programming/erasing. When the reset signal is accidentally input to the chip, a longer period in the reset state than usual (100 µs) is needed before the reset signal is released. 7. Switching of the MATs by FMATS should be needed when programming/erasing of the user boot MAT is operated in user-boot mode. The program which switches the MATs should be executed from the on-chip RAM. See section 20.
Table 20.
Storable /Executable Area On-chip RAM Item Embedded External Space Program (Expanded Mode) User MAT Storage Area User MAT Execution of Programming × Determination of Program Result × Operation for Program Error × Operation for FKEY Clear × Note: * Selected MAT × Transferring the data to the on-chip RAM enables this area to be used. Rev. 3.
Table 20.
Storable /Executable Area Item On-chip RAM Embedded External Space Program (Expanded Mode) User MAT Storage Area User MAT Operation for Erasure Error × Operation for FKEY Clear × Rev. 3.
Table 20.
Storable/Executable Area Item On-chip RAM User Boot External Space User MAT (Expanded Mode) MAT Operation for Settings of Program Parameter × Execution of Programming × Determination of Program Result × Operation for Program Error Selected MAT User Boot MAT Embedded Program Storage Area × ×*2 Operation for FKEY Clear × Switching MATs by FMATS × × Notes: 1. Transferring the data to the on-chip RAM enables this area to be used. 2.
Table 20.
Storable/Executable Area On-chip RAM Item User Boot External Space User MAT (Expanded Mode) MAT Execution of Erasure × Determination of Erasure Result × Operation for Erasure Error ×* Operation for FKEY Clear × Switching MATs by FMATS × Note: * Selected MAT User Boot MAT Embedded Program Storage Area × × Switching FMATS by a program in the on-chip RAM enables this area to be used. Rev. 3.
20.5 Protection There are three kinds of flash memory program/erase protection: hardware, software, and error protection. 20.5.1 Hardware Protection Programming and erasing of flash memory is forcibly disabled or suspended by hardware protection. In this state, the downloading of an on-chip program and initialization are possible.
20.5.2 Software Protection Software protection is set up in any of two ways: by disabling the downloading of on-chip programs for programming and erasing and by means of a key code. Table 20.10 Software Protection Function to be Protected Item Description Protection by the SCO bit • The program/erase-protected state is entered by clearing the SCO bit in FCCS which disables the downloading of the programming/erasing programs.
Error protection is cancelled only by a reset or by hardware-standby mode. Note that the reset should be released after the reset period of 100 µs which is longer than normal. Since high voltages are applied during programming/erasing of the flash memory, some voltage may remain after the error-protection state has been entered. For this reason, it is necessary to reduce the risk of damage to the flash memory by extending the reset period so that the charge is released.
20.6 Switching between User MAT and User Boot MAT It is possible to alternate between the user MAT and user boot MAT. However, the following procedure is required because these MATs are allocated to address 0. (Switching to the user boot MAT disables programming and erasing. Programming of the user boot MAT should take place in boot mode or programmer mode.) 1. MAT switching by FMATS should always be executed from the on-chip RAM. 2.
20.7 Programmer Mode Along with its on-board programming mode, this LSI also has a programmer mode as a further mode for the programming and erasing of programs and data. In the programmer mode, a generalpurpose PROM programmer can freely be used to write programs to the on-chip ROM. Program/erase is possible on the user MAT and user boot MAT*1. The PROM programmer must support microcomputers with 256 or 512-kbyte flash memory as a device type*2. Figure 20.18 shows a memory map in programmer mode.
20.8 Serial Communication Interface Specification for Boot Mode Initiating boot mode enables the boot program to communicate with the host by using the internal SCI. The serial communication interface specification is shown below. (1) Status The boot program has three states. 1. Bit-Rate-Adjustment State In this state, the boot program adjusts the bit rate to communicate with the host. Initiating boot mode enables starting of the boot program and entry to the bit-rate-adjustment state.
Reset Bit-rate-adjustment state Inquiry/response wait Response Inquiry Operations for inquiry and selection Transition to programming/erasing Operations for response Operations for erasing user MATs and user boot MATs Programming/erasing wait Checking Erasing Programming Operations for programming Operations for erasing Operations for checking Figure 20.19 Boot Program States Rev. 3.
(2) Bit-Rate-Adjustment State The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate has been adjusted, the boot program enters the inquiry and selection state. The bit-rate-adjustment sequence is shown in figure 20.20.
This response consists of 4 bytes of data. 1-byte command or 1-byte response Command or response n-byte Command or n-byte response Data Size Checksum Command or response Error response Error code Error response 128-byte programming Address Data (n bytes) Command Memory read response Size Checksum Data Response Checksum Figure 20.
(4) Inquiry and Selection States The boot program returns information from the flash memory in response to the host’s inquiry commands and sets the device code, clock mode, and bit rate in response to the host’s selection command. Inquiry and selection commands are listed below. Table 20.
the needed commands out of the commands and inquiries listed above. The boot program status inquiry command (H'4F) is valid after the boot program has received the programming/erasing transition command (H'40). (a) Supported Device Inquiry The boot program will return the device codes of supported devices and the product code in response to the supported device inquiry.
Response H'06 • Response, H'06, (1 byte): Response to the device selection command ACK will be returned when the device code matches. Error response H'90 ERROR • Error response, H'90, (1 byte): Error response to the device selection command ERROR : (1 byte): Error code H'11: Sum check error H'21: Device code error, that is, the device code does not match (c) Clock Mode Inquiry The boot program will return the supported clock modes in response to the clock mode inquiry.
Error Response H'91 ERROR • Error response, H'91, (1 byte) : Error response to the clock mode selection command • ERROR : (1 byte): Error code H'11: Checksum error H'22: Clock mode error, that is, the clock mode does not match. Even if the clock mode numbers are H'00 and H'01 by a clock mode inquiry, the clock mode must be selected using these respective values. (e) Multiplication Ratio Inquiry The boot program will return the supported multiplication and division ratios.
(f) Operating Clock Frequency Inquiry The boot program will return the number of operating clock frequencies, and the maximum and minimum values.
(g) User Boot MAT Information Inquiry The boot program will return the number of user boot MATs and their addresses.
(i) Erased Block Information Inquiry The boot program will return the number of erased blocks and their addresses. Command H'26 • Command, H'26, (1 byte): Inquiry regarding erased block information Response H'36 Size Number of blocks Block start address Block last address ··· SUM • Response, H'36, (1 byte): Response to the number of erased blocks and addresses • Size (three bytes): The number of bytes that represents the number of blocks, block-start addresses, and block-last addresses.
(k) New Bit-Rate Selection The boot program will set a new bit rate and return the new bit rate. This selection should be sent after sending the clock mode selection command.
• ERROR: (1 byte): Error code H'11: Sum checking error H'24: Bit-rate selection error The rate is not available. H'25: Error in input frequency This input frequency is not within the specified range. H'26: Multiplication-ratio error The ratio does not match an available ratio. H'27: Operating frequency error The frequency is not within the specified range. (5) Received Data Check The methods for checking of received data are listed below. 1.
4%. If the error is more than 4%, a bit rate error is generated. The error is calculated using the following expression: Error (%) = {[ φ × 106 (N + 1) × B × 64 × 2(2×n − 1) ] − 1} × 100 When the new bit rate is selectable, the rate will be set in the register after sending ACK in response. The host will send an ACK with the new bit rate for confirmation and the boot program will response with that rate.
(6) Transition to Programming/Erasing State The boot program will transfer the erasing program, and erase the user MATs and user boot MATs in that order. On completion of this erasure, ACK will be returned and will enter the programming/erasing state. The host should select the device code, clock mode, and new bit rate with device selection, clockmode selection, and new bit-rate selection commands, and then send the command for the transition to programming/erasing state.
5. After selection of the device and clock mode, inquiries for other required information should be made, such as the multiplication-ratio inquiry (H'22) or operating frequency inquiry (H'23), which are needed for a new bit-rate selection. 6. A new bit rate should be selected with the new bit-rate selection (H'3F) command, according to the returned information on multiplication ratios and operating frequencies. 7.
• Programming Programming is executed by a programming-selection command and a 128-byte programming command. Firstly, the host should send the programming-selection command and select the programming method and programming MATs. There are two programming selection commands, and selection is according to the area and method for programming. 1. User boot MAT programming selection 2.
(a) User boot MAT programming selection The boot program will transfer a programming program. The data is programmed to the user boot MATs by the transferred programming program. Command H'42 • Command, H'42, (1 byte): User boot MAT programming selection Response H'06 • Response, H'06, (1 byte): Response to user boot MAT programming selection When the programming program has been transferred, the boot program will return ACK.
• Command, H'50, (1 byte): 128-byte programming • Programming Address (4 bytes): Start address for programming Multiple of the size specified in response to the programming unit inquiry (i.e. H'00, H'01, H'00, H'00 : H'010000) • Programming Data (128 bytes): Data to be programmed The size is specified in the response to the programming unit inquiry.
• ERROR: (1 byte): Error code H'11: Checksum error H'2A: Address error H'53: Programming error An error has occurred in programming and programming cannot be continued. (10) Erasure Erasure is performed with the erasure selection and block erasure command. Firstly, erasure is selected by the erasure selection command and the boot program then erases the specified block. The command should be repeatedly executed if two or more blocks are to be erased.
(a) Erasure Selection The boot program will transfer the erasure program. User MAT data is erased by the transferred erasure program. Command H'48 • Command, H'48, (1 byte): Erasure selection Response H'06 • Response, H'06, (1 byte): Response for erasure selection After the erasure program has been transferred, the boot program will return ACK.
Command H'58 Size Block number SUM • Command, H'58, (1 byte): Erasure • Size, (1 byte): The number of bytes that represents the block number This is fixed to 1. • Block number (1 byte): H'FF Stop code for erasure • SUM (1 byte): Checksum Response H'06 • Response, H'06, (1 byte): Response to end of erasure (ACK) When erasure is to be performed after the block number H'FF has been sent, the procedure should be executed from the erasure selection command.
• ERROR: (1 byte): Error code H'11: Sum check error H'2A: Address error The read address is not in the MAT. H'2B: Size error The read size exceeds the MAT. (12) User Boot MAT Sum Check The boot program will return the byte-by-byte total of the contents of the bytes of the user boot MAT, as a 4-byte value.
Command H'4C • Command, H'4C, (1 byte): Blank check for user boot MAT Response H'06 • Response, H'06, (1 byte): Response to the blank check of user boot MAT If all user MATs are blank (H'FF), the boot program will return ACK. Error Response H'CC H'52 • Error Response, H'CC, (1 byte): Response to blank check for user boot MAT • Error Code, H'52, (1 byte): Erasure has not been completed. (15) User MAT Blank Check The boot program will check whether or not all user MATs are blank and return the result.
Table 20.13 Status Code Code Description H'11 Device Selection Wait H'12 Clock Mode Selection Wait H'13 Bit Rate Selection Wait H'1F Programming/Erasing State Transition Wait (Bit rate selection is completed) H'31 Programming State for Erasure H'3F Programming/Erasing Selection Wait (Erasure is completed) H'4F Programming Data Receive Wait (Programming is completed) H'5F Erasure Block Specification Wait (Erasure is completed) Table 20.
20.9 Usage Notes 1. The initial state of the product at its shipment is in the erased state. For the product whose revision of erasing is undefined, we recommend to execute automatic erasure for checking the initial state (erased state) and compensating. 2. For the PROM programmer suitable for programmer mode in this LSI and its program version, refer to the instruction manual of the socket adapter. 3.
key code area in programmer mode, a verification error will occur unless a software countermeasure is taken for the PROM programmer and the version of its program. 12. The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 2 kbytes or less. Accordingly, when the CPU clock frequency is 33 MHz, the download for each program takes approximately 120 µs at the maximum. 13.
Section 21 Boundary Scan (JTAG) The JTAG (Joint Test Action Group) is standardized as an international standard, IEEE Standard 1149.1, and is open to the public as IEEE Standard Test Access Port and Boundary-Scan Architecture. Although the name of the function is boundary scan and the name of the group who worked on standardization is the JTAG, the JTAG is commonly used as the name of a boundary scan architecture and a serial interface to access the devices having the architecture.
ETCK ETMS TAP controller Decoder ETRST ETDI Shift register SDBSR SDBPR SDIR SDIDR ETDO Mux [Legend] SDIR: SDBPR: SDBSR: SDIDR: Instruction register Bypass register Boundary scan register ID code register Figure 21.1 JTAG Block Diagram Rev. 3.
21.2 Input/Output Pins Table 21.1 shows the JTAG pin configuration. Table 21.1 Pin Configuration Pin Name Abbreviation I/O Function Test clock ETCK Input Test clock input Provides an independent clock supply to the JTAG. As the clock input to the ETCK pin is supplied directly to the JTAG, a clock waveform with a duty cycle close to 50% should be input. For details, see section 25, Electrical Characteristics. If there is no input, the ETCK pin is fixed to 1 by an internal pull-up.
21.3 Register Descriptions The JTAG has the following registers. • • • • Instruction register (SDIR) Bypass register (SDBPR) Boundary scan register (SDBSR) ID code register (SDIDR) Instructions can be input to the instruction register (SDIR) by serial transfer from the test data input pin (ETDI). Data from SDIR can be output via the test data output pin (ETDO). The bypass register (SDBPR) is a 1-bit register to which the ETDI and ETDO pins are connected in BYPASS, CLAMP, or HIGHZ mode.
21.3.1 Instruction Register (SDIR) SDIR is a 32-bit register. JTAG instructions can be transferred to SDIR by serial input from the ETDI pin. SDIR can be initialized when the ETRST pin is low or the TAP controller is in the Test-Logic-Reset state, but is not initialized by a reset or in standby mode. Only 4-bit instructions can be transferred to SDIR. If an instruction exceeding 4 bits is input, the last 4 bits of the serial data will be stored in SDIR.
• H8S/2167, H8S/2166 Bit Bit Name Initial Value R/W Description 31 30 29 28 TS3 TS2 TS1 TS0 1 1 1 0 R/W R/W R/W R/W Test Set Bits 0000: EXTEST mode 0001: Setting prohibited 0010: CLAMP mode 0011: HIGHZ mode 0100: SAMPLE/PRELOAD mode 0101: Setting prohibited : : 1101: Setting prohibited 1110: IDCODE mode (Initial value) 1111: BYPASS mode 27 to 14 All 0 R Reserved These bits are always read as 0 and cannot be modified. 13 1 R Reserved This bit is always read as 1 and cannot be modified.
21.3.2 Bypass Register (SDBPR) SDBPR is a 1-bit shift register. In BYPASS, CLAMP, or HIGHZ mode, SDBPR is connected between the ETDI and ETDO pins. 21.3.3 Boundary Scan Register (SDBSR) SDBSR is a shift register provided on the PAD for controlling the I/O terminals of this LSI. Using EXTEST mode or SAMPLE/PRELOAD mode, a boundary scan test conforming to the IEEE1149.1 standard can be performed. Table 21.3 shows the relationship between the terminals of this LSI and the boundary scan register. Rev. 3.
Table 21.3 Correspondence between Pins and Boundary Scan Register Pin No. Pin Name Input/Output Bit No.
Pin No. Pin Name Input/Output Bit No.
Pin No. Pin Name Input/Output Bit No.
Pin No. Pin Name Input/Output Bit No.
Pin No. Pin Name Input/Output Bit No.
Pin No. Pin Name Input/Output Bit No.
Pin No. Pin Name Input/Output Bit No.
Pin No. Pin Name Input/Output Bit No.
Pin No. Pin Name Input/Output Bit No. 128 P37 Input Enable Output 30 29 28 129 P40 Input Enable Output 27 26 25 130 P41 Input Enable Output 24 23 22 131 P42 Input Enable Output 21 20 19 132 P43 Input Enable Output 18 17 16 133 P52 Input Enable Output 15 14 13 134 P53 Input Enable Output 12 11 10 135 FWE Input 9 136 P54 Input Enable Output 8 7 6 137 P55 Input Enable Output 5 4 3 138 P44 Input Enable Output 2 1 0 to ETDO Note: The enable signals are active-high.
21.3.4 ID Code Register (SDIDR) SDIDR is a 32-bit register. In IDCODE mode, SDIDR can output H'0026200F (H8S/2168) or H'0030200F (H8S/2167 or H8S/2166), that are fixed codes, from ETDO. However, no serial data can be written to SDIDR via ETDI.
21.4 Operation 21.4.1 TAP Controller State Transitions Figure 21.2 shows the internal states of the TAP controller. State transitions basically conform to the IEEE1149.1 standard. 1 Test-logic-reset 0 Run-test/idle 0 1 1 1 Select-DR-scan 0 Select-IR-scan 0 1 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Capture-IR 0 0 Shift-IR 1 1 Exit1-IR 0 0 Pause-IR 1 0 Exit2-DR 1 Exit2-IR 1 Update-DR 0 1 Update-IR 1 0 Figure 21.2 TAP Controller State Transitions Rev. 3.
21.4.2 JTAG Reset The JTAG can be reset in two ways. • The JTAG is reset when the ETRST pin is held at 0. • When ETRST = 1, the JTAG can be reset by inputting at least five ETCK clock cycles while ETMS = 1. 21.5 Boundary Scan The JTAG pins can be placed in the boundary scan mode stipulated by the IEEE1149.1 standard by setting a command in SDIR. 21.5.1 Supported Instructions This LSI supports the three essential instructions defined in the IEEE1149.
EXTEST: Instruction code: B'0000 The EXTEST instruction is provided to test external circuitry when this LSI is mounted on a printed circuit board. When this instruction is executed, output pins are used to output test data (previously set by the SAMPLE/PRELOAD instruction) from the boundary scan register to the printed circuit board, and input pins are used to latch test results into the boundary scan register from the printed circuit board.
Notes: 1. Boundary scan mode does not cover power-supply-related pins (VCC, VCL, VSS, AVCC, AVSS, and AVref). 2. Boundary scan mode does not cover clock-related pins (EXTAL, XTAL, and PFSEL). 3. Boundary scan mode does not cover reset- and standby-related pins (RES, STBY, and RESO). 4. Boundary scan mode does not cover JTAG-related pins (ETCK, ETDI, ETDO, ETMS, and ETRST). 5. Fix the MD2 pin high. 6. Use the STBY pin in high state. Rev. 3.
21.6 Usage Notes 1. A reset must always be executed by driving the ETRST pin to 0, regardless of whether or not the JTAG is to be activated. The ETRST pin must be held low for 20 ETCK clock cycles. For details, see section 25, Electrical Characteristics. To activate the JTAG after a reset, drive the ETRST pin to 1 and specify the ETCK, ETMS, and ETDI pins to any value. If the JTAG is not to be activated, drive the ETRST, ETCK, ETMS, and ETDI pins to 1 or the high-impedance state.
9. If a pin with an open-drain function is sampled while its open-drain function is enabled and its corresponding output scan register is 1, 0 can be detected at the corresponding enable scan register. SDIR serial data input/output SDIR is captured into the shift register in Capture-IR, and bits 0 to 31 of SDIR are output in that order from the ETDO pin in Shift-IR. Data input from the ETDI pin is written to SDIR in Update-IR. ETDI ETDI Bit 0 ETDO Bit 31 . . . . . . . . . . .
SDIDR serial data input/output SDIDR is captured into the shift register in Capture-DR in IDCODE mode, and bits 0 to 31 of SDIDR are output in that order from the ETDO pin in Shift-DR. Data input from the ETDI pin is not written to any register in Update-DR. ETDI Shift register Bit 31 . . . . Bit 0 ETDO Bit 31 SDIDR Bit 0 Capture-DR Figure 21.5 Serial Data Input/Output (2) Rev. 3.
Section 22 Clock Pulse Generator This LSI incorporates a clock pulse generator which generates the system clock (φ), internal clock, bus master clock, and subclock (φSUB). The clock pulse generator consists of an oscillator, PLL multiplier circuit, system clock select circuit, medium-speed clock divider, bus master clock select circuit, subclock input circuit, and subclock waveform forming circuit. Figure 22.1 shows a block diagram of the clock pulse generator.
22.1 Oscillator Clock pulses can be supplied either by connecting a crystal resonator or by providing external clock input. 22.1.1 Connecting Crystal Resonator Figure 22.2 shows a typical method of connecting a crystal resonator. An appropriate damping resistance Rd, given in table 22.1, should be used. An AT-cut parallel-resonance crystal resonator should be used. Figure 22.3 shows the equivalent circuit of a crystal resonator. A crystal resonator having the characteristics given in table 22.
Table 22.2 Crystal Resonator Parameters Frequency(MHz) 5 8 10 12 16 20 25 RS (max) (Ω) 100 80 70 60 50 40 30 C0 (max) (pF) 7 7 7 7 7 7 7 22.1.2 External Clock Input Method Figure 22.4 shows a typical method of connecting an external clock signal. To leave the XTAL pin open, incidental capacitance should be 10 pF or less. To input an inverted clock to the XTAL pin, the external clock should be set to high in standby mode, subactive mode, subsleep mode, and watch mode.
22.2 PLL Multiplier Circuit The PLL multiplier circuit generates a clock of 1 or 4 times the frequency of its input clock. The PFSEL states and corresponding multiplier values are shown in table 22.5. Table 22.3 PFSEL and Multipliers Multiplier System Clock (MHz) 1 1 5 to 25 5 to 8.25 0 4 20 to 33 5 to 33 1 1 5 to 33 5 to 8.25 0 4 20 to 33 Input Clock (MHz) PFSEL Crystal Resonator 5 to 25 External Clock 22.
22.7 Clock Select Circuit The clock select circuit selects the system clock that is used in this LSI. A clock generated by the oscillator, to which the EXTAL and XTAL pins are input, and multiplied by the PLL circuit is selected as a system clock when returning from high-speed mode, mediumspeed mode, sleep mode, the reset state, or standby mode. In subactive mode, subsleep mode, or watch mode, a subclock input from the EXCL pin is selected as a system clock when the EXCLE bit in LPWRCR is 1.
22.8.3 Note on Operation Check This LSI may oscillate at several kHz of frequency even when a crystal resonator is not connected to the EXTAL and XTAL pins or an external clock is not input. Use this LSI after confirming that the LSI operates with appropriate frequency. Rev. 3.
Section 23 Power-Down Modes For operating modes after the reset state is cancelled, this LSI has not only the normal program execution state but also seven power-down modes in which power consumption is significantly reduced. In addition, there is also module stop mode in which reduced power consumption can be achieved by individually stopping on-chip peripheral modules. • Medium-speed mode System clock frequency for the CPU operation can be selected as φ/2, φ/4, φ/8, φ/16,or φ/32.
23.1 Register Descriptions Power-down modes are controlled by the following registers. To access SBYCR, LPWRCR, MSTPCRH, and MSTPCRL, the FLSHE bit in the serial timer control register (STCR) must be cleared to 0. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR).
Bit Bit Name Initial Value R/W Description 6 5 4 STS2 STS1 STS0 Standby Timer Select 2 to 0 0 0 0 R/W R/W R/W Select the wait time for clock settling from clock oscillation start when canceling software standby mode, watch mode, or subactive mode. Select a wait time of 8 ms (oscillation settling time) or more, depending on the operating frequency. With an external clock, select a wait time of 500 µs (external clock output settling delay time) or more, depending on the operating frequency. Table 23.
Table 23.1 Operating Frequency and Wait Time STS2 STS1 STS0 Wait Time 33M Hz 25M Hz 20 MHz 10 MHz 8 MHz 6 MHz Unit 0 0 0 8192 states 0.2 0.3 0.4 0.8 1.0 1.3 ms 0 0 1 16384 states 0.5 0.7 0.8 1.6 2.0 2.7 0 1 0 32768 states 1.0 1.3 1.6 3.3 4.1 5.5 0 1 1 65536 states 2.0 2.6 3.3 6.6 8.2 10.9 1 0 0 131072 states 4.0 5.2 6.6 13.1 16.4 21.8 1 0 1 262144 states 8.0 10.5 13.1 26.2 32.8 43.7 1 1 0 Reserved 1 1 1 16 states* 0.
Bit Bit Name Initial Value R/W Description 6 LSON 0 R/W Low-Speed On Flag Specifies the operating mode to be entered after executing the SLEEP instruction. This bit also controls whether to shift to highspeed mode or subactive mode when watch mode is cancelled.
Bit Bit Name Initial Value R/W Description 0 0 R/W Reserved The initial value should not be changed. 23.1.3 Module Stop Control Registers H, L, and A (MSTPCRH, MSTPCRL, MSTPCRA) MSTPCR specifies on-chip peripheral modules to shift to module stop mode in module units. Each module can enter module stop mode by setting the corresponding bit to 1. • MSTPCRH Bit Bit Name Initial Value R/W Corresponding Module 7 MSTP15 Reserved 0 R/W The initial value should not be changed.
• MSTPCRA Initial Value R/W Corresponding Module 7 to 3 MSTPA7 to MSTPA3 All 0 R/W Reserved 2 MSTPA2 0 R/W 14-bit PWM timer (PWMX_1) 1 MSTPA1 0 R/W 14-bit PWM timer (PWMX_0) 0 MSTPA0 0 R/W 8-bit PWM timer (PWM) Bit Bit Name The initial values should not be changed. MSTPCR sets operation and stop by the combination of bits as follows: MSTPCRH (bit 3) MSTPCRA (bit 2) MSTP11 MSTPA2 Function 0 0 14-bit PWM timer (PWMX_1) operates. 0 1 14-bit PWM timer (PWMX_1) stops.
23.1.4 Sub-Chip Module Stop Control Registers BH, BL (SUBMSTPBH, SUBMSTPBL) SUBMSTPB specifies on-chip peripheral modules to shift to module stop mode in module units. Each module can enter module stop mode by setting the corresponding bit to 1. • SUBMSTPBH Bit Bit Name Initial Value 7 to 0 SMSTPB15 All 1 to SMSTPB8 R/W Corresponding Module R/W Reserved The initial values should not be changed.
23.2 Mode Transitions and LSI States Figure 23.1 shows the enabled mode transition diagram. The mode transition from program execution state to program halt state is performed by the SLEEP instruction. The mode transition from program halt state to program execution state is performed by an interrupt. The STBY input causes a mode transition from any state to hardware standby mode. The RES input causes a mode transition from a state other than hardware standby mode to the reset state. Table 23.
Program halt state STBY pin = Low Hardware standby mode Reset state STBY pin = High RES pin = Low Program execution state RES pin = High SSBY = 0, LSON = 0 Sleep mode (main clock) SLEEP instruction High-speed mode (main clock) Any interrupt SCK2 to SCK0 are 0 SCK2 to SCK0 are not 0 Medium-speed mode (main clock) SLEEP instruction SLEEP instruction SSBY = 1, PSS = 1, DTON = 1, LSON = 1 Clock switching exception processing SLEEP instruction SSBY = 1, PSS = 1, DTON = 0 Watch mode (subclock) SLEEP inst
Table 23.
HighSpeed SubActive SubSleep Software Standby Hardware Standby Function- Halted ing/Halted (retained) (retained) Halted (retained) Halted (retained) Halted (retained) Halted (reset) SCI_0 to SCI_2 Function- Halted ing/Halted (retained/ (retained/ reset) reset) Halted (retained/ reset) Halted (retained/ reset) Halted (retained/ reset) PWM Function- Halted ing/Halted (reset) (reset) Halted (reset) Halted (reset) Halted (reset) Functioning Retained Retained Function Peripheral CRC Funct
23.3 Medium-Speed Mode The CPU makes a transition to medium-speed mode as soon as the current bus cycle ends according to the setting of the SCK2 to SCK0 bits in SBYCR. In medium-speed mode, the CPU operates on the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32) specified by the SCK2 to SCK0 bits. The bus masters other than the CPU (DTC) also operate in medium-speed mode when the DTSPEED bit in SBYCR is cleared to 0.
Medium-speed mode φ, peripheral module clock Bus master clock Internal address bus SBYCR SBYCR Internal write signal Figure 23.2 Medium-Speed Mode Timing 23.4 Sleep Mode The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0 and the LSON bit in LPWRCR is cleared to 0. In sleep mode, CPU operation stops but the peripheral modules do not stop. The contents of the CPU’s internal registers are retained.
23.5 Software Standby Mode The CPU makes a transition to software standby mode when the SLEEP instruction is executed with the SSBY bit in SBYCR set to 1, the LSON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) cleared to 0. In software standby mode, the CPU, on-chip peripheral modules, and clock pulse generator all stop.
Oscillator φ NMI NMIEG SSBY NMI exception Software standby mode handling (power-down mode) NMIEG = 1 SSBY = 1 SLEEP instruction Oscillation stabilization time tOSC2 NMI exception handling Figure 23.3 Software Standby Mode Application Example Rev. 3.
23.6 Hardware Standby Mode The CPU makes a transition to hardware standby mode from any mode when the STBY pin is driven low. In hardware standby mode, all functions enter the reset state. As long as the prescribed voltage is supplied, on-chip RAM data is retained. The I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low.
23.7 Watch Mode The CPU makes a transition to watch mode when the SLEEP instruction is executed in high-speed mode or subactive mode with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1. In watch mode, the CPU is stopped and peripheral modules other than WDT_1 are also stopped.
23.8 Subsleep Mode The CPU makes a transition to subsleep mode when the SLEEP instruction is executed in subactive mode with the SSBY bit in SBYCR cleared to 0, the LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1. In subsleep mode, the CPU is stopped. Peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1 are also stopped.
23.9 Subactive Mode The CPU makes a transition to subactive mode when the SLEEP instruction is executed in highspeed mode with the SSBY bit in SBYCR set to 1, the DTON bit and LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1. When an interrupt occurs in watch mode, and if the LSON bit in LPWRCR is 1, a direct transition is made to subactive mode. Similarly, if an interrupt occurs in subsleep mode, a transition is made to subactive mode.
23.10 Module Stop Mode Module stop mode can be individually set for each on-chip peripheral module. When the corresponding MSTP bit in MSTPCR and SUBMSTP is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. In turn, when the corresponding MSTP bit is cleared to 0, module stop mode is cancelled and the module operation resumes at the end of the bus cycle.
23.12 Usage Notes 23.12.1 I/O Port Status The status of the I/O ports is retained in software standby mode. Therefore, when a high level is output, the current consumption is not reduced by the amount of current to support the high level output. 23.12.2 Current Consumption when Waiting for Oscillation Settling The current consumption increases during oscillation settling. 23.12.
Section 24 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. • • • • 2. • • • • 3. • • Register Addresses (address order) Registers are listed from the lower allocation addresses. The MSB-side address is indicated for 16-bit addresses. Registers are classified by functional modules. The access size is indicated.
Address Module Data Bus Width Number of Access States Register Name Abbreviation Number of Bits Host interface control register_4 HICR4 8 H'FE00 LPC 16 2 BT status register_0 BTSR0 8 H'FE02 LPC 16 2 BT status register_1 BTSR1 8 H'FE03 LPC 16 2 BT control status register_0 BTCSR0 8 H'FE04 LPC 16 2 BT control status register_1 BTCSR1 8 H'FE05 LPC 16 2 BT control register BTCR 8 H'FE06 LPC 16 2 BT interrupt mask register 0 BTIMSR 8 H'FE07 LPC 16 2 SMIC fla
Module Data Bus Width Number of Access States Register Name Abbreviation Number of Bits Input data register 3 IDR3 8 H'FE20 LPC 16 2 Output data register 3 ODR3 8 H'FE21 LPC 16 2 Status register 3 STR3 8 H'FE22 LPC 16 2 LPC channel 3 address register H LADR3H 8 H'FE24 LPC 16 2 LPC channel 3 address register L LADR3L 8 H'FE25 LPC 16 2 SERIRQ control register 0 SIRQCR0 8 H'FE26 LPC 16 2 SERIRQ control register 1 SIRQCR1 8 H'FE27 LPC 16 2 Input data regist
Data Bus Width Number of Access States Register Name Abbreviation Number of Bits Sub-chip module stop control register SUBMSTPAH 8 H'FE3C SYSTEM 8 2 SUBMSTPAL 8 H'FE3D SYSTEM 8 2 SUBMSTPBH 8 H'FE3E SYSTEM 8 2 SUBMSTPBL 8 H'FE3F SYSTEM 8 2 Event count status register ECS 16 H'FE40 EVC 16 2 Event count control register ECCR 8 H'FE42 EVC 8 2 Module stop control register A MSTPCRA 8 H'FE43 SYSTEM 8 2 Noise canceler enable register P6NCE 8 H'FE44 PORT 8 2 Nois
Register Name Abbreviation Number of Bits Port D data direction register PDDDR 8 Address Data Bus Module Width Number of Access States H'FE4F PORT 8 2 (Write) Flash code control status register FCCS 8 H'FE88 FLASH 8 2 Flash program code select register FPCS 8 H'FE89 FLASH 8 2 Flash erase code select register FECS 8 H'FE8A FLASH 8 2 Flash key code register FKEY 8 H'FE8C FLASH 8 2 Flash MAT select register FMATS 8 H'FE8D FLASH 8 2 Flash transfer destination addr
Address Module Data Bus Width Number of Access States Register Name Abbreviation Number of Bits Second slave address register_2 SARX_2 8 H'FECA IIC_2 8 2 I C bus mode register_2 ICMR_2 8 H'FECB IIC_2 8 2 Slave address register_2 SAR_2 8 H'FECB IIC_2 8 2 PWMX (D/A) data register A_1 DADRA_1 16 H'FECC PWMX_1 8 4 PWMX (D/A) control register_1 DACR_1 8 H'FECC PWMX_1 8 2 PWMX (D/A) data register B_1 DADRB_1 16 H'FECE PWMX_1 8 4 PWMX (D/A) counter_1 DACNT_1 16 H'FECE
Address Module Data Bus Width Number of Access States Register Name Abbreviation Number of Bits DTC enable register A DTCERA 8 H'FEEE DTD 8 2 DTC enable register B DTCERB 8 H'FEEF DTC 8 2 DTC enable register C DTCERC 8 H'FEF0 DTC 8 2 DTC enable register D DTCERD 8 H'FEF1 DTC 8 2 DTC enable register E DTCERE 8 H'FEF2 DTC 8 2 DTC vector register DTVECR 8 H'FEF3 DTC 8 2 Address break control register ABRKCR 8 H'FEF4 INT 8 2 Break address register A BARA
Address Module Data Bus Width Number of Access States Register Name Abbreviation Number of Bits Serial control register_1 SCR_1 8 H'FF8A SCI_1 8 2 Transmit data register_1 TDR_1 8 H'FF8B SCI_1 8 2 Serial status register_1 SSR_1 8 H'FF8C SCI_1 8 2 Receive data register_1 RDR_1 8 H'FF8D SCI_1 8 2 Smart card mode register_1 SCMR_1 8 H'FF8E SCI_1 8 2 I C bus data register_1 ICDR_1 8 H'FF8E IIC_1 8 2 Second slave address register_1 SARX_1 8 H'FF8E IIC_1 8 2
Address Module Data Bus Width Number of Access States Register Name Abbreviation Number of Bits Serial status register_2 SSR_2 8 H'FFA4 SCI_2 8 2 Receive data register_2 RDR_2 8 H'FFA5 SCI_2 8 2 Smart card mode register_2 SCMR_2 8 H'FFA6 SCI_2 8 2 PWMX (D/A) counter _0 DACNT_0 16 H'FFA6 PWMX_0 8 4 PWMX (D/A) data register B_0 DADRB_0 16 H'FFA6 PWMX_0 8 4 Timer control/status register_0 TCSR_0 8 H'FFA8 WDT_0 16 2 WDT_0 16 2 WDT_0 16 2 WDT_0 16 2 H'FFAA
Address Module Data Bus Width Number of Access States Register Name Abbreviation Number of Bits Port 6 data register P6DR 8 H'FFBB PORT 8 2 Port B output data register PBODR 8 H'FFBC PORT 8 2 Port B input data register PBPIN 8 H'FFBD PORT 8 2 PORT 8 2 PORT 8 2 PORT 8 2 (Read) Port 8 data direction register P8DDR 8 H'FFBD (Write) Port 7 input data register P7PIN 8 H'FFBE (Read) Port B data direction register PBDDR 8 H'FFBE (Write) Port 8 data register P8DR 8
Address Module Data Bus Width Number of Access States Register Name Abbreviation Number of Bits PWM data polarity register B PWDPRB 8 H'FFD4 PWM 8 2 PWM data polarity register A PWDPRA 8 H'FFD5 PWM 8 2 PWM register select PWSL 8 H'FFD6 PWM 8 2 PWM data registers 15 to 0 PWDR15−0 8 H'FFD7 PWM 8 2 Serial mode register_0 SMR_0 8 H'FFD8 SCI_0 8 2 I C bus control register_0 ICCR_0 8 H'FFD8 IIC_0 8 2 Bit rate register_0 BRR_0 8 H'FFD9 SCI_0 8 2 I C bus status
Register Name Abbreviation Number of Bits A/D data register DH ADDRDH 8 Address Module Data Bus Width Number of Access States H'FFE6 8 2 8 2 8 2 8 2 WDT_1 16 2 WDT_1 16 2 WDT_1 16 2 WDT_1 16 2 A/D converter A/D data register DL ADDRDL 8 H'FFE7 A/D converter A/D control/status register ADCSR 8 H'FFE8 A/D converter A/D control register ADCR 8 H'FFE9 A/D converter Timer control/status register_1 TCSR_1 8 H'FFEA (read) Timer control/status register_1 TCSR_1 16
Address Module Data Bus Width Number of Access States Register Name Abbreviation Number of Bits Timer counter_X TCNT_X 8 H'FFF4 TMR_X 8 2 Timer counter_Y TCNT_Y 8 H'FFF4 TMR_Y 8 2 Time constant register C TCORC 8 H'FFF5 TMR_X 8 2 Timer input select register TISR 8 H'FFF5 TMR_Y 8 2 Time constant register A_X TCORA_X 8 H'FFF6 TMR_X 8 2 Time constant register B_X TCORB_X 8 H'FFF7 TMR_X 8 2 D/A data register 0 DADR0 8 H'FFF8 D/A 8 2 8 2 8 2 converter D/
24.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, so 16-bit registers are shown as 2 lines.
Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TWR14 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LPC TWR15 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IDR3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ODR3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 IBF3B OBF3B MWMF SWMF C/D3 DBU32 IBF3A OBF3A 2 STR3* DBU37 DBU36 DBU35 DBU34 C/D3 DBU32 IBF3A OBF3A LADR3H Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 B
Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ECS E15 E14 E13 E12 E11 E10 E9 E8 EVC E7 E6 E5 E4 E3 E2 E1 E0 ECCR EDSB ECSB3 ECSB2 ECSB1 ECSB0 MSTPCRA MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 SYSTEM P6NCE P67NCE P66NCE P65NCE P64NCE P63NCE P62NCE P61NCE P60NCE PORT P6NCMC P67NCMC P66NCMC P65NCMC P64NCMC P63NCMC P62NCMC P61NCMC P60NCMC P6NCCS NCCK2 NCCK1 NCCK0 PEODR PE7ODR
Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ICCR_5 ICE IEIC MST TRS ACKE BBSY IRIC SCP IIC_5 ICSR_5 ESTP STOP IRTR AASX AL AAS ADZ ACKB ICDR_5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SARX_5 SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX ICMR_5 MLS WAIT CKS2 CKS1 CKS0 BC2 BC1 BC0 SAR_5 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS ICCR_3 ICE IEIC MST TRS ACKE BBSY IRIC SCP ICSR_3 ESTP STOP IRTR AASX
Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ICSMBCR SMB5E SMB4E SME3E SMB2E SMB1E SMB0E FSEL1 FSEL0 IIC ICXR_2 STOPIM HNDS ICDRF ICDRE ALIE ALSL FNC1 FNC0 IIC_2 ICXR_3 STOPIM HNDS ICDRF ICDRE ALIE ALSL FNC1 FNC0 IIC_3 IICX3 TCSS IICX5 IICX4 IICX3 IIC ICXR_4 STOPIM HNDS ICDRF ICDRE ALIE ALSL FNC1 FNC0 IIC_4 ICXR_5 STOPIM HNDS ICDRF ICDRE ALIE ALSL FNC1 FNC0 IIC_5 KBCOMP EVENTE
Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module BCR2 ABWCP ASTCP ADFULLE EXCKS CPCSE BSC WSCR2 WMS10 WC11 WC10 WMS21 WMS20 WC22 WC21 WC20 PCSR PWCKX1B PWCKX1A PWCKX0B PWCKX0A PWCKX1C PWCKB PWCKA PWCKX0C PWM SYSCR2 P6PUE ADMXE SYSTEM SBYCR SSBY STS2 STS1 STS0 DTSPEED SCK2 SCK1 SCK0 LPWRCR DTON LSON NESEL EXCLE PNCCS PNCAH MSTPCRH MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8
Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ICRA Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 FRT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PAODR PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR PORT PAPIN PA7PIN PA6PIN PA5PIN PA4PIN PA3PIN PA2PIN PA1PIN PA0PIN PADDR PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR P1PCR P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR P2PCR P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR P3PCR P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P
Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCR_0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR_0, TCR_1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR_1 TCSR_0 CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0 TCSR_1 CMFB CMFA OVF OS3 OS2 OS1 OS0 TCORA_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCORA_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCORB_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ADDRAH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A/D ADDRAL AD1 AD0 converter ADDRBH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDRBL AD1 AD0 ADDRCH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDRCL AD1 AD0 ADDRDH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 ADDRDL AD1 AD0 ADCSR ADF ADIE ADST SCAN CKS CH2 CH1 CH0 ADCR TRGS1 TRGS0
Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCONRI ICST TMR TCONRS TMRX/Y Notes: 1. When TWRE = 1 or SELSTR3 = 0 2. When TWRE = 0 and SELSTR3 = 1 3. Some Bits have different names in normal mode and smart card interface mode. The Bit name in smart card interface mode is enclosed in parentheses. Rev. 3.
24.
Register High-Speed/ Abbrevia- Module Software Hardware tion Reset MediumSpeed Watch Sleep Sub-Active Sub-Sleep Stop Standby Standby Module STR3 Initialized Initialized LPC LADR3H Initialized Initialized LADR3L Initialized Initialized SIRQCR0 Initialized Initialized SIRQCR1 Initialized Initialized IDR1 ODR1 STR1 Init
Register High-Speed/ Abbrevia- Module Software Hardware tion Reset MediumSpeed Watch Sleep Sub-Active Sub-Sleep Stop Standby Standby Module P6NCE Initialized Initialized PORT P6NCMC Initialized Initialized P6NCCS Initialized Initialized PEODR Initialized Initialized PFODR Initialized Initialized PEPIN PEDDR Initialized Ini
Register High-Speed/ Abbrevia- Module Software Hardware tion Reset MediumSpeed Watch Sleep Sub-Active Sub-Sleep Stop Standby Standby Module ICCR_3 Initialized Initialized IIC_3 ICSR_3 Initialized Initialized ICDR_3 SARX_3 Initialized Initialized ICMR_3 Initialized Initialized SAR_3 Initialized Initialized ICCR_2 Initialized
Register High-Speed/ Abbrevia- Module Software Hardware tion Reset MediumSpeed Watch Sleep Sub-Active Sub-Sleep Stop Standby Standby Module ICRA Initialized Initialized INT ICRB Initialized Initialized ICRC Initialized Initialized ISR Initialized Initialized ISCRH Initialized Initialized ISCRL Initialized Initialized DTCERA Initialized
Register High-Speed/ Abbrevia- Module Software Hardware tion Reset MediumSpeed Watch Sleep Sub-Active Sub-Sleep Stop Standby Standby Module BRR_1 Initialized Initialized SCI_1 ISCR_1 Initialized Initialized IIC_1 SCR_1 Initialized Initialized SCI_1 TDR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized SSR_1 Initialized Initialized Initialized Initialized Ini
Register High-Speed/ Abbrevia- Module Software Hardware tion Reset MediumSpeed Watch Sleep Sub-Active Sub-Sleep Stop Standby Standby Module SCMR_2 Initialized Initialized SCI_2 DADRB_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized PWMX_0 DACNT_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized TCSR_0 Initialized Initialized TCNT_0 Initialized
Register High-Speed/ Abbrevia- Module Software Hardware tion Reset MediumSpeed Watch Sleep Sub-Active Sub-Sleep Stop Standby Standby Module SYSCR Initialized Initialized SYSTEM MDCR Initialized Initialized BCR Initialized Initialized WSCR Initialized Initialized TCR_0 Initialized Initialized TCR_1 Initialized Initialized TCSR_0 Initialized
HighSpeed/ Register Abbrevia- Software Hardware tion Reset MediumSpeed Watch Sleep SubActive Sub-Sleep Stop Module Standby Standby Module ADDRBH Initialized Initialized Initialized Initialized Initialized Initialized Initialized A/D ADDRBL Initialized Initialized Initialized Initialized Initialized Initialized Initialized ADDRCH Initialized Initialized Initialized Initialized Initialized Initialized Initialized ADDRCL Initialized Initialized
Rev. 3.
Section 25 Electrical Characteristics 25.1 Absolute Maximum Ratings Table 25.1 lists the absolute maximum ratings. Table 25.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage* VCC –0.3 to +4.3 V Input voltage (except port 7, 8, C0 to C5, D6, and D7) Vin –0.3 to VCC +0.3 Input voltage (port 7) Vin –0.3 to AVCC +0.3 Input voltage (port 8, C0 to C5, D6, and D7) Vin –0.3 to +7.0 Reference power supply voltage AVref –0.3 to AVCC +0.3 Analog power supply voltage AVCC –0.
25.2 DC Characteristics Table 25.2 lists the DC characteristics. Table 25.3 lists the permissible output currents. Table 25.4 lists the bus drive characteristics. Table 25.2 DC Characteristics (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC*1 = 3.0 V to 3.6 V, AVref*1 = 3.0 V to AVCC, VSS = AVSS*1 = 0 V Item Schmitt trigger input voltage Typ. Max. Test Unit Conditions VCC × 0.2 V VCC × 0.7 VCC × 0.05 Symbol Min.
Item Symbol Min. Typ. Max. Test Unit Conditions 0.5 IOH = –200 µA CLKRUN, GA20, PME, LSMI, LSCI, SERIRQ, LAD3 to LAD0 VCC × 0.9 IOH = –0.5 mA Output pins other than (4) above VCC –0.5 IOH = –200 µA VCC –1.0 IOH = –1 mA Output SCL5 to SCL0, SDA5 to 3 SDA0* high voltage Port 8, C0 to C5, D6, D7, 4 SCK2 to SCK0* (4) VOH 0.5 IOL = 8 mA 0.4 IOL = 3 mA VCC × 0.1 IOL = 1.5 mA Output pins other than (5) above 0.4 IOL = 1.
Test Symbol Min. Typ. Max. Unit Conditions Item 1.0 2.0 mA 2.5 5.0 µA 0.1 1.0 mA During A/D, D/A conversion 0.5 5.0 A/D, D/A conversion standby 0.5 5.0 µA Analog power supply current During A/D, D/A conversion Reference power supply current During A/D conversion AIcc A/D, D/A conversion standby AIref Input All input pin capacitance Cin 10 pF RAM standby voltage VRAM 3.0 V VCC start voltage VCCSTART 0 0.
Table 25.3 Permissible Output Currents Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V Item Symbol Min. Permissible output low current SCL5 to SCL0, SDA5 to SDA0 IOL (per pin) Ports 1, 2, and 3 Other output pins Typ. Max. Unit 10 mA 5 1.
25.3 AC Characteristics Figure 25.3 shows the test conditions for the AC characteristics. 3V RL LSI output pin C C = 30pF : All ports RL = 2.4 kΩ RH = 12 kΩ I/O timing test levels • Low level : 0.8 V • High level : 1.5 V RH Figure 25.3 Output Load Circuit 25.3.1 Clock Timing Table 25.4 shows the clock timing. The clock timing specified here covers clock output (φ) and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation stabilization times.
Table 25.5 External Clock Input Conditions Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 5 MHz to 33 MHz Item Symbol Min. Max. Unit Test Conditions External clock input low level pulse width tEXL 10 ns Figure 25.7 External clock input high level pulse width tEXH 10 ns External clock input rising time tEXr 5 ns External clock input falling time tEXf 5 ns Clock low level pulse width tCL 0.4 0.6 tcyc Clock high level pulse width tCH 0.4 0.
VCC STBY tOSC1 tOSC1 RES φ Figure 25.5 Oscillation Stabilization Timing φ NMI IRQi ( i = 0 to 15 ) KINi ( i = 0 to 15 ) tOSC2 WUEi ( i = 8 to 15 ) Figure 25.6 Oscillation Stabilization Timing (Exiting Software Standby Mode) tEXH tEXL VCC × 0.5 EXTAL tEXr tEXf Figure 25.7 External Clock Input Timing Rev. 3.
VCC 2.7 V STBY VIH EXTAL φ (Internal and external) RES tDEXT* Note: The external clock output stabilization delay time (tDEXT) includes a RES pulse width (tRESW). Figure 25.8 Timing of External Clock Output Stabilization Delay Time tEXCLH tEXCLL VCC × 0.5 EXCL tEXCLr tEXCLf Figure 25.9 Subclock Input Timing Rev. 3.
25.3.2 Control Signal Timing Table 25.7 shows the control signal timing. Only external interrupts NMI, IRQ0 to IRQ15, KIN0 to KIN15, and WUE8 to WUE15 can be operated based on the subclock (φSUB = 32.768 kHz). Table 25.7 Control Signal Timing Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 5 MHz to 33 MHz Item Symbol Min. Max. Unit Test Conditions RES setup time tRESS 200 ns Figure 25.
φ tNMIS tNMIH NMI tNMIW IRQi (i = 0 to 15) tIRQW tIRQS tIRQH IRQ Edge input tIRQS IRQ Level input KINi (i = 0 to 15) WUEi (i = 8 to 15) tIRQW tIRQS tIRQH KIN, WUE Edge input Figure 25.11 Interrupt Input Timing Rev. 3.
25.3.3 Bus Timing Table 25.8 shows the bus timing. In subclock (φSUB = 32.768 kHz) operation, external expansion mode operation cannot be guaranteed. Table 25.8 Bus Timing Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 5 MHz to 33 MHz Item Symbol Min. Max. Unit Test Conditions Address delay time tAD 15 ns Figures 25.12 to 25.16 Address setup time tAS 0.5 × tcyc –15 Address hold time tAH 0.
T1 T2 φ tAD A23 to A0, IOS* CS256, CPCS1 tCSD tAS tAH tASD tASD AS* tRSD1 RD (Read) tRSD2 tACC2 tAS tACC3 tRDS tRDH D15 to D0 (Read) tWRD2 HWR, LWR (Write) tWRD2 tAS tAH tWDD tWSW1 tWDH D15 to D0 (Write) Note: * AS is multiplexed with IOS. Either the AS or IOS function can be selected by the IOSE bit of SYSCR. Figure 25.12 Basic Bus Timing/2-State Access Rev. 3.
T1 T3 T2 φ tAD A23 to A0, IOS* CS256, CPCS1 tCSD tAS tAH tASD tASD AS* tRSD1 tRSD2 tACC4 RD (Read) tAS tRDS tACC5 tRDH D15 to D0 (Read) tWRD1 tWRD2 HWR, LWR (Write) tAH tWDD tWDS tWSW2 tWDH D15 to D0 (Write) Note: * AS is multiplexed with IOS. Either the AS or IOS function can be selected by the IOSE bit of SYSCR. Figure 25.13 Basic Bus Timing/3-State Access Rev. 3.
T1 Tw T2 T3 φ A23 to A0, IOS* CS256, CPCS1 AS* RD (Read) D15 to D0 (Read) HWR, LWR (Write) D15 to D0 (Write) tWTS tWTH tWTS tWTH WAIT Note: * AS is multiplexed with IOS. Either the AS or IOS function can be selected by the IOSE bit of SYSCR. Figure 25.14 Basic Bus Timing/3-State Access with One Wait State Rev. 3.
T1 T1 T2 or T3 T2 φ tAD A23 to A0, IOS* CS256, CPCS1 tAS tAH tASD tASD AS* tRSD2 RD (Read) tACC3 tRDS D15 to D0 (Read) Note: * AS is multiplexed with IOS. Either the AS or IOS function can be selected by the IOSE bit of SYSCR. Figure 25.15 Burst ROM Access Timing/2-State Access Rev. 3.
T1 T2 or T3 T1 φ tAD A23 to A0, IOS* CS256, CPCS1 AS* tRSD2 RD (Read) tACC1 tRDS tRDH D15 to D0 (Read) Note: * AS is multiplexed with IOS. Either the AS or IOS function can be selected by the IOSE bit of SYSCR. Figure 25.16 Burst ROM Access Timing/1-State Access Rev. 3.
25.3.4 Multiplex Bus Timing Table 25.9 shows the Multiplex bus interface timing. In subclock (φSUB = 32.768 kHz) operation, external expansion mode operation cannot be guaranteed. Table 25.9 Multiplex Bus Timing Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 5 MHz to 33 MHz Item Symbol Min.. Max. Unit Test Conditions Address delay time tAD — 15 ns Figures 25.17, Address setup time 2 tAS2 0.5 × tcyc − 15 — Address hold time 2 tAH2 1.
T1 T3 T2 T4 φ tCSD IOS, CS256, CPCS1 tAHD AH tRSD1 tRSD2 tACC2 RD (Read) tRDS tACC6 AD15 to AD0 (Read) D15 to D0 A15 to A0 tAS2 tAD tRDH tAH2 tWRD2 tWRD2 tWSW1 HWR, LWR (Write) tAD tWDD AD15 to AD0 (Write) tWDH D15 to D0 A15 to A0 Figure 25.
25.3.5 Timing of On-Chip Peripheral Modules Tables 25.10 to 25.13 show the on-chip peripheral module timing. The on-chip peripheral modules that can be operated by the subclock (φSUB = 32.768 kHz) are I/O ports, external interrupts (NMI, IRQ0 to IRQ15, KIN0 to KIN15, and WUE8 to WUE15), watchdog timer, and 8-bit timer (channels 0 and 1) only. Rev. 3.
Table 25.10 Timing of On-Chip Peripheral Modules Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ SUB = 32.768 kHz*, φ = 5 MHz to 33 MHz Item Symbol Min. Max. Unit Test Conditions I/O ports Output data delay time tPWD 30 ns Figure 25.19 Input data setup time tPRS 20 Input data hold time tPRH 20 Timer output delay time tFTOD 30 ns Figure 25.20 Timer input setup time tFTIS 20 Timer clock input setup time tFTCS 20 Timer clock pulse width Single edge tFTCWH 1.
T2 T1 φ tPRS tPRH Ports 1 to 9 and A to F (read) tPWD Ports 1 to 6, 8, 9 and A to F (write) Figure 25.19 I/O Port Input/Output Timing φ tFTOD FTOA, FTOB tFTIS FTIA, FTIB, FTIC, FTID Figure 25.20 FRT Input/Output Timing φ tFTCS FTCI tFTCWH tFTCWL Figure 25.21 FRT Clock Input Timing φ tTMOD TMO_0, TMO_1 TMO_X, TMO_Y Figure 25.22 8-Bit Timer Output Timing Rev. 3.
φ tTMCS tTMCS TMI_0, TMI_1 TMI_X, TMI_Y tTMCWL tTMCWH Figure 25.23 8-Bit Timer Clock Input Timing φ tTMRS TMI_0, TMI_1 TMI_X, TMI_Y Figure 25.24 8-Bit Timer Reset Input Timing φ tPWOD PW15 to PW0, PWX3 to PWX0 Figure 25.25 PWM, PWMX Output Timing tSCKW tSCKr tSCKf SCK0 to SCK2 tScyc Figure 25.26 SCK Clock Input Timing Rev. 3.
SCK0 to SCK2 tTXD TxD0 to TxD2 (transmit data) tRXS tRXH RxD0 to RxD2 (receive data) Figure 25.27 SCI Input/Output Timing (Clock Synchronous Mode) φ tTRGS ADTRG Figure 25.28 A/D Converter External Trigger Input Timing φ tRESD tRESD RESO tRESOW Figure 25.29 WDT Output Timing (RESO) Rev. 3.
Table 25.11 I2C Bus Timing Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 5 MHz to 33 MHz Item Symbol Min. Typ. Max. Unit Test Conditions SCL input cycle time tSCL 12 tcyc Figure 25.30 SCL input high pulse width tSCLH 3 SCL input low pulse width 5 tSCLL SCL, SDA input rise time tSr 7.5* SCL, SDA input fall time tSf 300 SCL, SDA output fall time tOf 20 + 0.
SDA0 to SDA5 VIH VIL tBUF tSCLH tSTAH tSP tSTAS tSTOS SCL0 to SCL5 P* S* Sr* tSCLL tSf P* tSr tSCL tSDAS tSDAH Note: * S, P, and Sr indicate the following conditions: S: Start condition P: Stop condition Sr: Retransmission start condition Figure 25.30 I2C Bus Interface Input/Output Timing Table 25.12 LPC Module Timing Conditions: VCC = 3.0 V to 3.6V, VSS = 0 V, φ = 5 MHz to 33 MHz Item Symbol Min. Typ. Max. Unit Test Conditions Input clock cycle tLcyc 30 ns Figure 25.
tLCKH tLcyc LCLK tLCKL LCLK tTXD LAD3 to LAD0, SERIRQ, CLKRUN (Transmit signal) tRXS tRXH LAD3 to LAD0, SERIRQ, CLKRUN, LFRAME (Receive signal) tOFF LAD3 to LAD0, SERIRQ, CLKRUN (Transmit signal) Figure 25.31 LPC Interface (LPC) Timing Table 25.13 JTAG Timing Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 5 MHz to 33 MHz Item Symbol Min. Max. Unit Test Conditions ETCK clock cycle time tTCKcyc 40* 200* ns Figure 25.
tTCKcyc tTCKH tTCKf ETCK tTCKL tTCKr Figure 25.32 JTAG ETCK Timing ETCK tRSTHW RES ETRST tTRSTW Figure 25.33 Reset Hold Timing ETCK tTMSS tTMSH tTDIS tTDIH ETMS ETDI tTDOD ETDO Figure 25.34 JTAG Input/Output Timing Rev. 3.
25.4 A/D Conversion Characteristics Table 25.14 lists the A/D conversion characteristics. Table 25.14 A/D Conversion Characteristics (AN7 to AN0 Input: 134/266-State Conversion) Condition A: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, AVref = 3.0 V to AVCC VSS = AVSS = 0 V, φ = 5 MHz to 16 MHz Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, AVref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 5 MHz to 33 MHz Condition A Item Min. Resolution Typ. Condition B Max. Min. 10 Typ. Max.
25.5 D/A Conversion Characteristics Table 25.15 lists the D/A conversion characteristics. Table 25.15 D/A Conversion Characteristics Condition: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, AVref = 3.0 V to AVCC VSS = AVSS = 0 V, φ = 5 MHz to 33 MHz Item Min. Typ. Max. Unit Resolution 8 8 8 Bits Conversion time Load capacitance 20 pF 10 µs Absolute accuracy Load resistance 2 MΩ ±2.0 ±3.0 LSB Load resistance 4 MΩ ±2.0 Rev. 3.
25.6 Flash Memory Characteristics Table 25.16 lists the flash memory characteristics. Table 25.16 Flash Memory Characteristics Condition: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Avref = 3.0 V to AVCC, VSS = AVSS =0V Ta = 0°C to +75°C (operating temperature range for programming/erasing in regular specifications) Ta = 0°C to +85°C (operating temperature range for programming/erasing in widerange specifications) • H8S/2168 Item Symbol Programming time*1*2*4 tP 1 2 4 Erase time* * * tE Min. Typ.
• H8S/2167 Item Symbol Programming time*1*2*4 tP 1 2 4 Erase time* * * tE Min. Typ. Max. Unit 3 30 ms/128 bytes 80 800 ms/4-kbyte block 500 5000 ms/32-kbyte block 1000 10000 ms/64-kbyte block Test Conditions Programming time (total)*1*2*4 Σ tP 7.5 22.5 s/384 kbytes Ta = 25°C Erase time (total)*1*2*4 Σ tE 7.5 22.
• H8S/2166 Item Symbol Programming time*1*2*4 tP 1 2 4 Erase time* * * tE Min. Typ. Max.
25.7 Usage Notes It is necessary to connect a bypass capacitor between the VCC pin and VSS pin and a capacitor between the VCL pin and VSS pin for stable internal step-down power. An example of connection is shown in figure 25.35. Vcc power supply Bypass capacitor 10 µF VCC External capacitor for internal step-down power stabilization VCL One 0.1 µF / 0.47 µF or two in parallel 0.01 µF VSS VSS It is recommended that a bypass capacitor be connected to the VCC pin.
Appendix A.
Port Name Pin Name MCU Operating Mode Port 95 to 93 (EXPE = 1) Reset Hardware Software Standby Standby Mode Mode Watch Sleep Mode Mode Subsleep Subactive Mode Mode T T H H H H AS/IOS, HWR/RD AS/IOS, HWR/RD kept kept kept kept I/O port I/O port kept kept kept kept CPCS1/ CPCS1/ I/O port I/O port AS, IOS, Program Execution State HWR, RD (EXPE = 0) Port 92 and 91 (EXPE = 1) T T CPCS1 (EXPE = 0) Port 90 (EXPE = 1) T T H/kept H/kept H/kept H/kept LWR (EXPE = 0) Port A
B. Product Lineup Product Type Type Code Mark Code Package (Code) H8S/2168 HD64F2168 F2168VTE33 144-pin TQFP (TFP-144) H8S/2167 HD64F2167 F2167VTE33 H8S/2166 HD64F2166 F2166VTE33 F-ZTAT version Rev. 3.
C. Package Dimensions For package dimensions, dimensions described in Renesas Semiconductor Packages have priority. Unit: mm 18.0 ± 0.2 16 108 73 72 144 37 0.4 18.0 ± 0.2 109 0.08 *Dimension including the plating thickness Base material dimension 0.10 ± 0.05 0.15 ± 0.04 *0.17 ± 0.05 1.0 1.00 0.07 M 0.16 ± 0.04 1.20 Max 36 1 *0.18 ± 0.05 1.0 0° – 8° 0.5 ± 0.1 Package Code JEDEC EIAJ Weight (reference value) Figure C.1 Package Dimensions (TFP-144) Rev. 3.
Main Revisions and Additions in this Edition Item Page Revisions (See Manual for Details) Section 5 Interrupt Controller 100 Section 5.7.4 added. 305 • Cascading of TMR_0 and TMR_1 (Cascading of TMR_Y and TMR_X is not allowed) 5.7.4 Note on IRQ Status Registers (ISR16, ISR) Section 12 8-bit Timer 12.1 Features Operation as a 16-bit timer can be performed using TMR_0 as the upper half and TMR_1 as the lower half (16-bit count mode).
Item Page Revisions (See Manual for Details) Section 14 Serial Communication Interface (SCI) 352 Feature of asynchronous mode added. 14.3.10 Serial Interface Control register (SCICR) 375 • Average transfer rate generator (SCI_0 and SCI_2): 460.606 kbps or 115.152 kbps selectable at 10.667MHz operation; 720 kbps, 460.784 kbps, 230.392 kbps, or 115.196 kbps selectable at 16- or 24-MHz operation; 230.392 kbps or 115.
Item Page Revisions (See Manual for Details) Transmission: 417, 418 Deleted Reception: The output waveform can also be inverted using the IrTxINV bit in SCICR. Deleted Here, the input waveform can also be inverted using the IrRxINV bit in SCICR. Section 15 I2C Bus Interface (IIC) 505 Added 717 Modified 15.6 Usage Notes Section 21 Boundary Scan (JTAG) 6. Use the STBY pin in high state. 21.5.
Item Page Revisions (See Manual for Details) Table 25.2 DC Characteristics (2) 785 Description amended. Item Symbol Current Normal ICC consumption operation 5 * Sleep mode Standby 6 mode* 25.3 AC Characteristics 25.3.3 Bus Timing 794, 800 Table 25.8 Bus Timing Min. Typ. Max. Unit 43 55 mA 30 40 38 90 120 µA Description amended. Item Symbol Min. Max. Unit Write data hold time tWDH 0.5 × tcyc – 5 ns 25.3.4 Multiplex Bus Timing Table 25.
Index 14-bit PWM timer (PWMX)................... 261 16-bit count mode................................... 326 16-bit free-running timer (FRT) ............. 277 16-bit, 2-state access space ..................... 129 16-bit, 3-state access space ..................... 132 256-kbyte expansion area ....................... 116 8-bit PWM timer (PWM)........................ 251 8-bit timer (TMR) ................................... 305 8-bit, 2-state access space .......................
CRCDOR.........................429, 754, 765, 776 Crystal oscillator..................................... 722 D/A converter ......................................... 589 DACR.............................266, 591, 754, 761, .........................................765, 771, 776, 781 DADR..............................591, 761, 771, 781 DADRA ..................................... 754, 765, 776 DADRB ..................................... 754, 765, 776 DAR........................................................
Interrupt exception handling..................... 68 Interrupt exception handling sequence ..... 94 Interrupt exception handling vector table ............................................... 85 Interrupt mask bit...................................... 26 Interval timer mode................................. 345 IrDA........................................................ 417 IRQ15 to IRQ0 interrupts ......................... 82 ISCR ......................................................... 77 ISCR16H .........
P6NCCS ..........................207, 752, 764, 775 P6NCE.............................206, 752, 764, 775 P6NCMC .........................207, 752, 764, 775 P7PIN ..............................213, 758, 769, 779 P8DDR ............................217, 758, 769, 779 P8DR ...............................217, 758, 769, 779 P9DDR ............................222, 758, 769, 779 P9DR ...............................223, 758, 769, 779 PADDR ...........................226, 757, 769, 779 PAODR ...........................
SDIR ....................................................... 701 SEMR ............................. 376, 754, 765, 776 Serial communication interface (SCI) .... 351 Serial communication interface specification............................................ 670 Serial data reception ....................... 389, 403 Serial data transmission .................. 387, 401 Serial formats.......................................... 465 Shift instructions....................................... 36 Single mode ............
Rev. 3.
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2168 Group Publication Date: 1st Edition, Dec, 2002 Rev.3.00, Mar 12, 2004 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd. 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str.
H8S/2168Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0078-0300Z
