Datasheet

Section 27 Electrical Characteristics
Rev. 3.00 Mar 21, 2006 page 753 of 788
REJ09B0300-0300
Table 27.23 Timing of On-Chip Peripheral Modules (2)
Condition A: V
CC
= 5.0 V ±10%, V
CC
B = 5.0 V ±10%, V
SS
= 0 V,
φ = 2 MHz to maximum operating frequency,
T
a
= –20 to +75°C (normal specification product),
T
a
= –40 to +85°C (wide range temperature specification product)
Condition B: V
CC
= 4.0 V to 5.5 V, V
CC
B = 4.0 V to 5.5 V, V
SS
= 0 V,
φ = 2 MHz to maximum operating frequency,
T
a
= –20 to +75°C (normal specification product),
T
a
= –40 to +85°C (wide range temperature specification product)
Condition C: V
CC
= 2.7 V to 3.6 V, V
CC
B = 2.7 V to 5.5 V, V
SS
= 0 V, φ = 2 MHz to maximum
operating frequency, T
a
= –20 to +75°C
Condition
A
Condition
B
Condition
C
10 MHz 16 MHz 20 MHz
Item Symbol Min Max Min Max Min Max Unit
Test
Conditions
CS/HA0 setup time t
HAR
10 — 10 — 10 —
CS/HA0 hold time t
HRA
10 — 10 — 10 —
IOR pulse width t
HRPW
220 — 120 — 120 —
HDB delay time t
HRD
— 200 — 100 — 100
HDB hold time t
HRF
040025025
HIF
read
cycle
HIRQ delay time t
HIRQ
— 200 — 120 — 120
CS/HA0 setup time t
HAW
10 — 10 — 10 —
CS/HA0 hold time t
HWA
10 — 10 — 10 —
IOW pulse width t
HWPW
100 — 60 — 60 —
HDB
setup
time
Fast A20
gate not
used
50 — 30 — 30 —
HIF
write
cycle
Fast A20
gate used
t
HDW
85 — 55 — 45 —
HDB hold time t
HWD
25 — 15 — 15 —
GA20 delay time t
HGA
— 180 — 90 — 90
ns Figure
27.27