Datasheet

Section 27 Electrical Characteristics
Rev. 3.00 Mar 21, 2006 page 747 of 788
REJ09B0300-0300
Bus Timing: Table 27.22 shows the bus timing. Operation in external expansion mode is not
guaranteed when operating on the subclock (φ = 32.768 kHz).
Table 27.22 Bus Timing (1) (Normal Mode)
Condition A: V
CC
= 5.0 V ±10%, V
CC
B = 5.0 V ±10%, V
SS
= 0 V, φ = 2 MHz to maximum
operating frequency, T
a
= –20 to +75°C (normal specification product),
T
a
= –40 to +85°C (wide range temperature specification product)
Condition B: V
CC
= 4.0 V to 5.5 V, V
CC
B = 4.0 V to 5.5 V, V
SS
= 0 V, φ = 2 MHz to maximum
operating frequency, T
a
= –20 to +75°C (normal specification product),
T
a
= –40 to +85°C (wide range temperature specification product)
Condition C: V
CC
= 2.7 V to 3.6 V, V
CC
B = 2.7 V to 5.5 V, V
SS
= 0 V, φ = 2 MHz to maximum
operating frequency, T
a
= –20 to +75°C
Condition A Condition B Condition C
10 MHz 16 MHz 20 MHz
Item Symbol Min Max Min Max Min Max Unit
Test
Conditions
Address delay
time
t
AD
— 40 — 30 — 20 ns
Address
setup time
t
AS
0.5 ×
t
cyc
– 30
— 0.5 ×
t
cyc
– 20
— 0.5 ×
t
cyc
– 15
— ns
Address hold
time
t
AH
0.5 ×
t
cyc
– 20
— 0.5 ×
t
cyc
– 15
— 0.5 ×
t
cyc
– 10
— ns
CS delay time
(IOS)
t
CSD
— 40 — 30 — 20 ns
AS delay time t
ASD
— 60 — 45 — 30 ns
RD delay
time 1
t
RSD1
— 60 — 45 — 30 ns
RD delay
time 2
t
RSD2
— 60 — 45 — 30 ns
Read data
setup time
t
RDS
35 — 20 — 15 — ns
Read data
hold time
t
RDH
0 — 0 — 0 — ns
Read data
access time 1
t
ACC1
— 1.0 ×
t
cyc
– 60
— 1.0 ×
t
cyc
– 40
— 1.0 ×
t
cyc
– 30
ns
Read data
access time 2
t
ACC2
— 1.5 ×
t
cyc
– 50
— 1.5 ×
t
cyc
– 35
— 1.5 ×
t
cyc
– 25
ns
Figures
27.11 to
27.15